ZHCSR67 July 2020 DRV8353M
PRODUCTION DATA
Bypass the VM pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 μF. Place this capacitor as near to the VM pin as possible with a thick trace or ground plane connected to the GND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be electrolytic. This capacitance must be at least 10 μF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk capacitance should be placed such that it minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for VDRAIN, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VDRAIN pins and VGLS and GNDs. These capacitors should be 1 μF, rated for 16 V, and be of type X5R or X7R.
Bypass the DVDD pin to the GND/DGND pin with a 1-μF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or X7R. Place this capacitor as near to the pin as possible and minimize the path from the capacitor to the GND/DGND pin.
The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if a significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND. Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the low-side MOSFET source back to the SPx/SLx pins.