ZHCSJ76A March 2018 – April 2019 DRV8343-Q1
PRODUCTION DATA.
IC1 Control is shown in Figure 49 and described in Table 21.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLR_FLT | PWM_MODE | 1PWM_COM | 1PWM_DIR | 1PWM_BRAKE | |||
| R/W-0b | R/W-000b | R/W-0b | R/W-0b | R/W-00b | |||
| Bit | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | CLR_FLT | R/W | 0b |
Write a 1 to this bit to clear all latched fault bits. This bit automatically resets after being written |
| 6-4 | PWN_MODE | R/W | 000b |
000b = 6x PWM mode 001b = 3x PWM mode 010b = 1x PWM mode 011b = Independent half-bridge (for all phases) 100b = Phases A and B are independent half-bridges, Phase C is independent FET 101b = Phases B and C are independent half-bridges, Phase A is independent FET 110b = Phase A is independent half-bridge, Phases B and C are independent FET 111b =Independent FET (for all phases) |
| 3 | 1PWM_COM | R/W | 0b |
0b = 1x PWM mode uses synchronous rectification 1b = 1x PWM mode uses asynchronous rectification (diode freewheeling) |
| 2 | 1PWM_DIR | R/W | 0b |
In 1x PWM mode this bit is OR’ed with the INHC (DIR) input |
| 1-0 | 1PWM_BRAKE | R/W | 00b |
00b = Outputs follow commanded inputs 01b = Turn on all three low-side MOSFETs 10b = Turn on all three high-side MOSFETs 11b = Turn off all six MOSFETs (coast) |