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ZHCSJU7 May 2019 DRV8340-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PHP|48
- MPQF051B

散熱焊盤機械數據 (封裝 | 引腳)

PHP|48
- PPTD117D

訂購信息

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
GATE DRIVER
Power supply pin voltage (VM)	–0.3	65	V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)	–0.3	0.3	V
MOSFET drain sense pin voltage (VDRAIN)	–0.3	65	V
Charge pump pin voltage (CPH, VCP)	–0.3	V_VM + 13.5	V
Charge-pump negative-switching pin voltage (CPL)	–0.3	V_VM	V
Internal logic regulator pin voltage (DVDD)	–0.3	3.8	V
Voltage difference between VM and VDRAIN	–10	10	V
Digital pin voltage (ENABLE, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS, nDIAG)	–0.3	5.75	V
Continuous high-side gate drive pin voltage (GHx)	–5⁽²⁾	V_VCP + 0.5	V
Transient 200-ns high-side gate drive pin voltage (GHx)	–7	V_VCP + 0.5	V
High-side gate drive pin voltage with respect to SHx (GHx)	–0.3	13.5	V
Continuous high-side source sense pin voltage (SHx, DLx)	–5⁽²⁾	V_VM + 5	V
Transient 200-ns high-side source sense pin voltage (SHx, DLx)	–7	V_VM + 7	V
Continuous high-side source sense pin voltage (SHx, DLx)	–5⁽²⁾	V_DRAIN + 5	V
Transient 200-ns high-side source sense pin voltage (SHx, DLx)	–7	V_DRAIN + 7	V
Continuous low-side gate drive pin voltage (GLx)	–0.5	15	V
Gate drive pin source current (GHx, GLx)	Internally limited		A
Gate drive pin sink current (GHx, GLx)	Internally limited		A
Continuous low-side source sense pin voltage (SLx)	–1	1	V
Transient 200-ns low-side source sense pin voltage (SLx)	–3	3	V
Push-pull output buffer reference voltage (VSDO)	–0.3	5.75	V
Push-pull output current (SDO)	0	10	mA
Open drain pullup voltage (nFAULT)	–0.3	5.75	V
Open drain output current (nFAULT)	0	10	mA
Operating junction temperature, T_J	–40	150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Continuous high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to –2 V minimum for an absolute maximum of 65 V on VM. At 60 V and below, the full specification of –5 V continuous on GHx and SHx is allowable.