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ZHCSJU7 May 2019 DRV8340-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PHP|48
- MPQF051B

散熱焊盤機械數據 (封裝 | 引腳)

PHP|48
- PPTD117D

訂購信息

8.3.4 Gate Driver Protective Circuits

The DRV8340-Q1 device is protected against VM undervoltage, charge pump undervoltage, MOSFET VDS overcurrent, gate driver shorts, and overtemperature events. The DRV8340-Q1 device also provides a detection mechanism for open-load, offline short-to-supply, and offline short-to-ground conditions. When a fault occurs, the individual fault bit is set high along with the global FAULT bit in the FAULT status register for the SPI device. The FAULT bit is OR’ed with all the other individual status bits. In the H/W device, only the nFAULT pin is driven low during a fault condition. Some of the protection and detection features can be disabled through SPI in the SPI device, or the nDIAG pin in the H/W device

Table 10. Fault Action and Response

FAULT	CONDITION	CONFIGURATION	REPORT	GATE DRIVER	LOGIC	RECOVERY
VM undervoltage (UVLO)	V_VM < V_UVLO	—	nFAULT	Hi-Z	Disabled	Automatic: V_VM > V_UVLO
Charge pump undervoltage (CPUV)	V_VCP < V_CPUV	DIS_CPUV = 0b	nFAULT	Hi-Z	Active	Automatic: V_VCP > V_CPUV
Charge pump undervoltage (CPUV)	V_VCP < V_CPUV	DIS_CPUV = 1b	None	Active	Active	Automatic: V_VCP > V_CPUV
V_DS overcurrent (VDS_OCP)	V_DS > V_{VDS_OCP}	OCP_MODE = 00b	nFAULT	Hi-Z	Active	Latched: CLR_FLT, ENABLE Pulse
		OCP_MODE = 01b	nFAULT	Hi-Z	Active	Retry: t_RETRY
		OCP_MODE = 10b	nFAULT	Active	Active	Report only
		OCP_MODE = 11b	None	Active	Active	No action
Gate driver fault (GDF)	Gate voltage stuck > t_DRIVE	DIS_GDF = 0b	nFAULT	Hi-Z	Active	Latched: CLR_FLT, ENABLE Pulse
Gate driver fault (GDF)	Gate voltage stuck > t_DRIVE	DIS_GDF = 1b	None	Active	Active	No action
Thermal warning (OTW)	T_J > T_OTW	OTW_REP = 0b	None	Active	Active	No action
Thermal warning (OTW)	T_J > T_OTW	OTW_REP = 1b	nFAULT	Active	Active	Automatic: T_J< T_OTW – T_HYS
Thermal shutdown (OTSD)	T_J > T_OTSD	OTSD_MODE = 0b	nFAULT	Hi-Z	Active	Latched: CLR_FLT, ENABLE Pulse
Thermal shutdown (OTSD)	T_J > T_OTSD	OTSD_MODE = 1b	nFAULT	Hi-Z	Active	Automatic: T_J < T_OTSD – T_HYS
Open load passive (OLP)	No load detected	EN_OLP = 0b	None	Hi-Z	Active	No action
Open load passive (OLP)	No load detected	EN_OLP = 1b	nFAULT	Hi-Z	Active	Report only
Open load active (OLA)	No load detected	EN_OLA_X = 0b	None	Active	Active	No action
Open load active (OLA)	No load detected	EN_OLA_X = 1b	nFAULT	Active	Active	Report only
Offline short-to-supply (SHT_BAT)	Phase node short-to-supply	EN_SHT_TST = 0b	None	Hi-Z	Active	No action
Offline short-to-supply (SHT_BAT)	Phase node short-to-supply	EN_SHT_TST = 1b	nFAULT	Hi-Z	Active	Report only
Offline short-to-ground (SHT_GND)	Phase node short-to-ground	EN_SHT_TST = 0b	None	Hi-Z	Active	No action
Offline short-to-ground (SHT_GND)	Phase node short-to-ground	EN_SHT_TST = 1b	nFAULT	Hi-Z	Active	Report only
Device internal memory ⁽¹⁾data fault	Memory checksum fault detected	—	nFAULT	Active	Active	No action

(1) The DRV8340-Q1 has a OTP (one time program) memory which stores TI internal data used for analog functional blocks. The memory has a check-sum feature, and nFAULT is pulled low if a fault is detected at power up.