ZHCSJU7 May 2019 DRV8340-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1
Three Phase Smart Gate Drivers
- 8.3.1.1
PWM Control Modes
- 8.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)
- 8.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)
- 8.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)
- 8.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)
- 8.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)
- 8.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is 75 kΩ to DVDD)
- 8.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is 18 kΩ to DVDD)
- 8.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)
- 8.3.1.2 Device Interface Modes
- 8.3.1.3 Gate Driver Voltage Supplies
- 8.3.1.4 Smart Gate Drive Architecture
- 8.3.1.1
PWM Control Modes
- 8.3.2 DVDD Linear Voltage Regulator
- 8.3.3 Pin Diagrams
- 8.3.4
Gate Driver Protective Circuits
- 8.3.4.1 VM Supply Undervoltage Lockout (UVLO)
- 8.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)
- 8.3.4.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 8.3.4.4 Gate Driver Fault (GDF)
- 8.3.4.5 Thermal Warning (OTW)
- 8.3.4.6 Thermal Shutdown (OTSD)
- 8.3.4.7 Open Load Detection (OLD)
- 8.3.4.8 Offline Shorts Diagnostics
- 8.3.4.9 Reverse Supply Protection
- 8.3.1
Three Phase Smart Gate Drivers
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 Status Registers
- 8.6.2
Control Registers
- 8.6.2.1 IC1 Control Register (Address = 0x04) [reset = 0x00]
- 8.6.2.2 IC2 Control Register (address = 0x05) [reset = 0x40]
- 8.6.2.3 IC3 Control Register (Address = 0x06) [reset = 0xFF]
- 8.6.2.4 IC4 Control Register (Address = 0x07) [reset = 0xFF]
- 8.6.2.5 IC5 Control Register (Address = 0x08) [reset = 0xFF]
- 8.6.2.6 IC6 Control Register (Address = 0x09) [reset = 0x99]
- 8.6.2.7 IC7 Control Register (Address = 0x0A) [reset = 0x99]
- 8.6.2.8 IC8 Control Register (Address = 0x0B) [reset = 0x99]
- 8.6.2.9 IC9 Control Register (Address = 0x0C) [reset = 0x2F]
- 8.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]
- 8.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]
- 8.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]
- 8.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]
- 8.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.4.7.1 Open Load Detection in Passive Mode (OLP)
In open load detection in passive mode, open load diagnosis is performed without the motor in motion. If the motor is disconnected from the device an open load is detected and the nFAULT pin will latch low until a clear faults command is issued by the MCU either through the CLR_FLT bit or an ENABLE reset pulse. The fault also clears when the device is power cycled or comes out of sleep mode. OLP is designed for applications having capacitance less than the values listed in Table 11 between motor phase pins to ground.
Table 11. Open Load Passive Diagnostic Run-Time
| Capacitance (nF) | OLP_SHTS_DLY (ms) |
|---|---|
| 5 | 0.25 |
| 26 | 1.25 |
| 110 | 5 |
| 270 | 11.5 |
When the open load test is running, all external MOSFETs are disabled. For the H/W device option, at power-up or after going from sleep mode, the offline short-to-supply (SHT_BAT) and short-to-ground (SHT_GND) diagnostics run first followed by the OLP diagnostic if the nDIAG pin is left as no connect or tied to GND. If the nDIAG pin is tied to DVDD (or an external 3.3 V) the open load test is not performed. If a short condition is detected, the OLP diagnostic is not run (see Offline Shorts Diagnostics). If a short condition and open load occurs on a given phase at device power-up, for example, only the short condition is reported on the nFAULT pin and through the SPI fault register. In the SPI device option the OLP test is performed when commanded through SPI. If both short and OLP diagnostics are enabled simultaneously and a short condition is detection, only the short condition is reported on the nFAULT pin and through the SPI fault register.
The sequence to perform open load diagnostics in passive mode is as follows:
- Device powered up (ENABLE = 1).
- Mode is selected by SPI.
- Hi-Z all three half-bridges by turning-off all the external MOSFETs.
- Write a 1 to the EN_OLP bit in the SPI register and OLP is performed.
- If an open load is detected, the nFAULT pin is driven low, and the FAULT bit, the OLD bit, and the respective OL_PH_x bit are latched high. When the open load condition is removed, a clear faults command must be issued by the MCU either through the CLR_FLT bit or an ENABLE reset pulse which resets the OL_PH_x register bit and causes the nFAULT pin to go high.
- If open load is not detected, the EN_OLP bits return to default setting (0b) after tOL expires.
The EN_OLP register keeps the written command until the diagnostic is complete. The half bridges must stay in Hi-Z state for the entire duration of the test. While open load diagnostic is running, if an input change occurs or the EN_OLP bit is set low, the open load test is aborted to start normal operation again, and no fault is reported. OLP should not be performed if the motor is energized.
The open load detection checks for a high impedance connection on the motor phase pins (SHx or DLx). The diagnostic has two major steps as listed in the OLP Steps section. The sequencing of the pullup and pulldown current varies depending on the load connections. Figure 28 a simplified H-bridge configuration as an example for open load detection.
Figure 28. Circuit for Open Load Detection in Passive Mode