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ZHCSF68D May 2015 – July 2019 DRV8305-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PHP|48
- MPQF051B

散熱焊盤機械數據 (封裝 | 引腳)

PHP|48
- PPTD394

訂購信息

6.1 Absolute Maximum Ratings

over operating temperature range with respect to GND (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Power supply pin voltage (PVDD)		–0.3	45	V
Power supply pin voltage ramp rate (PVDD)		0	2	V/µs
High-side charge pump pin voltage (VCPH)		–0.3	PVDD + 12	V
Low-side regulator pin voltage (VCP_LSD)		–0.3	12	V
Charge pump 1 positive switching pin voltage (CP1H)		PVDD – 1.5	PVDD + 12	V
Charge pump 2 positive switching pin voltage (CP2H)		PVDD – 3	PVDD + 12	V
Charge pump negative switching pin voltage (CPxL)		–0.3	PVDD	V
High-side gate driver pin voltage (GHx)		–5	57	V
Gate-to-source voltage difference (GHx-SHx), (GLx-SLx)		–0.3	15	V
Low-side gate driver pin voltage (GLx)		–3	12	V
High-side gate driver source voltage (SHx)		–5	45	V
Transient 200-ns high-side gate driver source voltage (SHx)		–7	45	V
High-side gate driver source voltage (SHx)		–5	PVDD + 5	V
Low-side gate driver source voltage (SLx)		–3	5	V
Transient 200-ns low-side gate driver source voltage (SLx)		–5	5	V
Drain pin voltage (VDRAIN)		–0.3	45	V
Control pin voltage (INHx, INLx, EN_GATE, SCLK, SDI, SCS, SDO, nFAULT, PWRGD)		–0.3	5.5	V
Wake pin voltage (WAKE)		–0.3	45	V
Sense amplifier voltage (SPx, SNx)		–3	5	V
Transient 200-ns sense amplifier voltage (SPx, SNx)		–5	5	V
Sense amplifier output pin voltage (SOx)		–0.3	5.5	V
Externally applied reference voltage, DRV8305N (VREG)		–0.3	5.5	V
Externally applied reference sink current, DRV8305N (VREG)		0	100	µA
Internal digital regulator voltage (DVDD)		–0.3	3.6	V
Internal analog regulator voltage (AVDD)		–0.3	5.5	V
Open drain pins sink current (nFAULT, PWRGD)		0	7	mA
Wake pin sink current (WAKE) – limit current with external resistor		0	1	mA
Junction temperature, T_J	DRV8305xQPHPQ1	–40	150	°C
Junction temperature, T_J	DRV8305xEPHPQ1⁽²⁾⁽³⁾	–40	175	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) IC is designed to be operational up to T_J = 175°C. Internal overtemperature shutdown will be disabled by default on the DRV8305xEPHPQ1.

(3) Because lifetime degrades exponentially at higher temperatures, operation between T_J = 150°C to 175°C must be limited to transient and infrequent events. For transient events between T_J = 150°C to 175°C for a total of 10 hours over lifetime, no degradation in lifetime is expected. Contact TI for lifetime impact if the use case requires T_J = 150°C to 175°C greater than 10 hours.