ZHCSF68D May 2015 – July 2019 DRV8305-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Integrated Three-Phase Gate Driver
- 7.3.2 INHx/INLx: Gate Driver Input Modes
- 7.3.3 VCPH Charge Pump: High-Side Gate Supply
- 7.3.4 VCP_LSD LDO: Low-Side Gate Supply
- 7.3.5 GHx/GLx: Half-Bridge Gate Drivers
- 7.3.6 DVDD and AVDD: Internal Voltage Regulators
- 7.3.7 VREG: Voltage Regulator Output
- 7.3.8 Protection Features
- 7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Status Registers
- 7.6.2
Control Registers
- 7.6.2.1 HS Gate Drive Control (Address = 0x5)
- 7.6.2.2 LS Gate Drive Control (Address = 0x6)
- 7.6.2.3 Gate Drive Control (Address = 0x7)
- 7.6.2.4 IC Operation (Address = 0x9)
- 7.6.2.5 Shunt Amplifier Control (Address = 0xA)
- 7.6.2.6 Voltage Regulator Control (Address = 0xB)
- 7.6.2.7 VDS Sense Control (Address = 0xC)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.5 Limp Home or Fail Code Operation
The DRV8305-Q1 enables the adoption of secondary limp-home or fail code software through configurable fault mode handling. The following device features may be configured during the operating state without stopping the motor.
- IDRIVE Gate Current Output (IDRIVEN_HS, IDRIVEP_HS, IDRIVEN_LS, IDRIVEP_LS): All four IDRIVEX settings may be adjusted during normal operation without issue. This features allows the software to change the slew rate, switching characteristics of the external MOSFETs on the fly if required without having to stop the motor rotation. The IDRIVEX settings are located in the SPI registers 0x5 (high-side) and 0x6 (low-side).
- VDS Fault Mode (VDS_MODE): The VDS overcurrent monitors may be changed from latched shutdown (VDS_MODE = b'000) or report only (VDS_MODE = b'001) modes to disabled (VDS_MODE = b'010) mode to allow operation of the external MOSFETs past normal operating conditions. This is the only VDS_MODE change allowed in the operating state. The VDS_MODE setting is located in the SPI register 0xC, bits D2-D0.
- VDS Comparator Thresholds (VDS_LEVEL): The VDS overcurrent monitor threshold (VDS_LEVEL) may be changed at any time during operation to allow for higher than standard operating currents. The VDS_LEVEL setting is located in the SPI register 0xC.
- VGS Fault Mode (DIS_GDRV_FAULT): The VGS fault detection monitors can be disabled through the SPI register 0x9, bit D8. Reporting in SPI will also be disabled as a result.
- SNS_OCP Fault Mode (DIS_SNS_OCP): The sense amplifier overcurrent monitors can be disabled through the SPI register 0x9, bit D4. Reporting in SPI will also be disabled as a result.
- PVDD Undervoltage Lockout (DIS_VPVDD_UVLO2): The main power supply undervoltage lockout can be disabled through the SPI register 0x9, but D9. Reporting in SPI will also be disabled as a result.
- OTSD Overtemperature Shutdown (FLIP_OTS): The overtemperature shutdown can be disabled through the SPI register 0x9, bit D10. Reporting in SPI will also be disabled as a result. The OTS overtemperature shutdown is disabled by default on the Grade 0, DRV8305xE device.
Figure 16. Operating States