ZHCSF68D May 2015 – July 2019 DRV8305-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Integrated Three-Phase Gate Driver
- 7.3.2 INHx/INLx: Gate Driver Input Modes
- 7.3.3 VCPH Charge Pump: High-Side Gate Supply
- 7.3.4 VCP_LSD LDO: Low-Side Gate Supply
- 7.3.5 GHx/GLx: Half-Bridge Gate Drivers
- 7.3.6 DVDD and AVDD: Internal Voltage Regulators
- 7.3.7 VREG: Voltage Regulator Output
- 7.3.8 Protection Features
- 7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Status Registers
- 7.6.2
Control Registers
- 7.6.2.1 HS Gate Drive Control (Address = 0x5)
- 7.6.2.2 LS Gate Drive Control (Address = 0x6)
- 7.6.2.3 Gate Drive Control (Address = 0x7)
- 7.6.2.4 IC Operation (Address = 0x9)
- 7.6.2.5 Shunt Amplifier Control (Address = 0xA)
- 7.6.2.6 Voltage Regulator Control (Address = 0xB)
- 7.6.2.7 VDS Sense Control (Address = 0xC)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
6.6 SPI Timing Requirements (Slave Mode Only)
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| tSPI_READY | SPI read after power on | PVDD > VPVDD_UVLO1 | 5 | 10 | ms | |
| tCLK | Minimum SPI clock period | 100 | ns | |||
| tCLKH | Clock high time | 40 | ns | |||
| tCLKL | Clock low time | 40 | ns | |||
| tSU_SDI | SDI input data setup time | 20 | ns | |||
| tHD_SDI | SDI input data hold time | 30 | ns | |||
| tD_SDO | SDO output data delay time, CLK high to SDO valid | CL = 20 pF | 20 | ns | ||
| tHD_SDO | SDO output hold time | 40 | ns | |||
| tSU_SCS | SCS setup time | 50 | ns | |||
| tHD_SCS | SCS hold time | 50 | ns | |||
| tHI_SCS | SCS minimum high time before SCS active low | 400 | ns | |||
| tACC | SCS access time, SCS low to SDO out of high impedance | 10 | ns | |||
| tDIS | SCS disable time, SCS high to SDO high impedance | 10 | ns | |||
Figure 1. SPI Slave Mode Timing Definition