ZHCSF68D May 2015 – July 2019 DRV8305-Q1
PRODUCTION DATA.
The DRV8305-Q1 uses a linear regulator to generate the proper gate-to-source voltage vias for the low-side N-channel MOSFETs. The linear regulator generates a fixed 10-V supply voltage with respect to GND. When enabled, the gate of the external MOSFET is connected to VCPH_LSD through the internal gate drivers. In order to support automotive cold crank transients the input voltage for the VCP_LSD linear regulator is taken from the VCPH charge pump. This allows the DRV8305-Q1 to provide sufficient VGS to drive standard and logic level MOSFETs during the low voltage transient.
The low-side regulator is disabled until EN_GATE is set high to reduce unneeded power consumption by the IC. After EN_GATE is set high, the device will go through a power up sequence for the gate drivers and gate drive supplies. 1 ms should be allocated after EN_GATE is set high to allow the low-side regulator to reach its regulation voltage. The VCP_LSD regulator is continuously monitored for undervoltage conditions to prevent underdriven MOSFET scenarios. If an undervoltage condition is detected the appropriate actions is taken and reported through the SPI registers.