ZHCSF68D May 2015 – July 2019 DRV8305-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Integrated Three-Phase Gate Driver
- 7.3.2 INHx/INLx: Gate Driver Input Modes
- 7.3.3 VCPH Charge Pump: High-Side Gate Supply
- 7.3.4 VCP_LSD LDO: Low-Side Gate Supply
- 7.3.5 GHx/GLx: Half-Bridge Gate Drivers
- 7.3.6 DVDD and AVDD: Internal Voltage Regulators
- 7.3.7 VREG: Voltage Regulator Output
- 7.3.8 Protection Features
- 7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Status Registers
- 7.6.2
Control Registers
- 7.6.2.1 HS Gate Drive Control (Address = 0x5)
- 7.6.2.2 LS Gate Drive Control (Address = 0x6)
- 7.6.2.3 Gate Drive Control (Address = 0x7)
- 7.6.2.4 IC Operation (Address = 0x9)
- 7.6.2.5 Shunt Amplifier Control (Address = 0xA)
- 7.6.2.6 Voltage Regulator Control (Address = 0xB)
- 7.6.2.7 VDS Sense Control (Address = 0xC)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PHP|48
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- PHP|48
訂購信息
7.4.1 Power Up Sequence
The DRV8305-Q1 has an internal state machine to ensure proper power up and power down sequencing of the device. When PVDD power is applied the device will remain inactive until PVDD cross the digital logic threshold. At this point, the digital logic will become active, VREG will enable (if 3.3-V or 5-V device option is used), the passive gate pulldowns will enable, and nFAULT will be driven low to indicate that the device has not reached the VPVDD_UVLO2 threshold. nFAULT will remain driven low until PVDD crosses the PVDD_UVLO threshold. At this point the device will enter its standby state.
Figure 15. Power-Up Sequence