SNLS579A April 2018 – November 2018 DP83TC811S-Q1
PRODUCTION DATA.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | SGMII TX/RX Buffer Half-Full Threshold | RGMII RX Clock Internal Delay | RGMII TX Clock Internal Delay | Reserved | RGMII Mode | Reserved | |
| RO-0 | RW-0 | RW/Strap | RW/Strap | RW-0 | RW/Strap | RW-0 | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Clock Select | Reserved | RMII Mode | RMII Revision Select | RMII Overflow Status | RMII Underflow Status | RMII Receive Elasticity Buffer Size | |
| RW/Strap | RW-1 | RW/Strap | RW-0 | RO/COR-0 | RO/COR-0 | RW-01 | |
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 15 | Reserved | RO | 0 | Reserved |
| 14:13 | SGMII TX/RX Buffer Half-Full Threshold | RW | 10 | SGMII Buffer Half-Full Threshold:
00 = 5-bit 01 = 2-bit 10 = 6-bit 11 = 10-bit |
| 12 | RGMII RX Clock Internal Delay | RW | Strap | RGMII RX Clock Internal Delay:
1 = Receive path internal clock delay is enabled 0 = Receive path internal clock delay is disabled Note: When enabled, receive path internal clock (RX_CLK) is delayed by 2ns relative to receive data. When disabled, data and clock are in align mode. |
| 11 | RGMII TX Clock Internal Delay | RW | Strap | RGMII TX Clock Internal Delay:
1 = Transmit path internal clock delay is enabled 0 = Transmit path internal clock delay is disabled Note: When enabled, transmit path internal clock (TX_CLK) is delayed by 2ns relative to transmit data. When disabled, data and clock are in align mode. |
| 10 | Reserved | RW | 0 | Reserved |
| 9 | RGMII Mode | RW | Strap | RGMII Mode Enable:
1 = Enable RGMII mode of operation 0 = Mode determined by Bit[5] |
| 8 | Reserved | RW | 0 | Reserved |
| 7 | Clock Select | RW | Strap | Reference Clock Select:
Strap determines the clock reference requirement. 1 = 50-MHz clock reference, CMOS-level oscillator 0 = 25-MHz clock reference, crystal or CMOS-level oscillator |
| 6 | Reserved | RW | 1 | Reserved |
| 5 | RMII Mode | RW | Strap | RMII Mode Enable:
1 = Enable RMII mode of operation 0 = Enable MII mode of operation |
| 4 | RMII Revision Select | RW | 0 | RMII Revision Select:
1 = RMII Revision 1.0 0 = RMII Revision 1.2 RMII revision 1.0, CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet. RMII revision 1.2, CRS_DV will toggle at the end of a packet to indicate de-assertion of CRS. |
| 3 | RMII Overflow Status | RO, COR | 0 | RX FIFO Overflow Status:
1 = Normal 0 = Overflow detected |
| 2 | RMII Underflow Status | RO, COR | 0 | RX FIFO Underflow Status:
1 = Normal 0 = Underflow detected |
| 1:0 | RMII Receive Elasticity Buffer Size | RW | 01 | Receive Elasticity Buffer Size:
This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50-MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at ±100ppm accuracy. 00 = 5-bit tolerance (up to 8750 byte packets) 01 = 2-bit tolerance (up to 1250 byte packets) 10 = 3-bit tolerance (up to 3750 byte packets) 11 = 4-bit tolerance (up to 6250 byte packets) |