SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The registers in these regions are used to push descriptors into queues, to pop descriptors from queues, and to retrieve information from queues.
| Offset | Name | Description |
|---|---|---|
| 0x00000000 + 16×N | Queue N Register A
(0 – 8191) |
The Queue N Register A is an optional register that is implemented only for a queue if the queue supports entry / byte count feature. The entry count feature provides a count of the number of entries that are currently valid in the queue. |
| 0x00000004 + 16×N | Queue N Register B
(0 – 8191) |
The Queue N Register B is an optional register that is implemented only for a queue if the queue supports a total byte count feature. The total byte count feature provides a count of the total number of bytes in all of the packets that are currently valid in the queue. This register must be read prior to reading Queue N Register D during packet pop operation if the total size information is desired. |
| 0x00000008 + 16×N | Queue N Register C
(0 – 8191) |
The Queue N Register C is used to provide additional information about the packet that is being pushed or popped from the queue. This register provides an option for the packet to be pushed onto either the tail of the queue (default) or the head of the queue (override). This register must be written prior to writing the Queue N register D during packet write operations. This register must be read prior to reading Queue N register D during pop operations if the packet size information is desired. |
| 0x0000000C + 16×N | Queue N Register D
(0 – 8191) |
The Queue N Register D is written to add a packet to the queue and read to pop a packet off a queue. The packet is pushed or popped to/from the queue only when the Queue Register D is written. |
NOTE
There are three sets of Registers A, B, C, and D (for all 8191 queues), one set in each of the following QMSS regions: Queue Management, Queue Proxy and Queue Peek. The functioning of these registers is different in each region. See Section 4.1.5 for details on the Queue Peek registers.
The following sections describe each of the four register locations that are present for each queue in these regions. For reasons of implementation and area efficiency, these registers are not actually implemented as a huge array of flip flops but are instead implemented as a single set of mailbox registers that use the LSBs of the provided address as a queue index. Because of this implementation, all accesses to these registers need to be performed as a single burst write for each packet add or a single burst read for each packet pop operation. For host (user application) access, this requires writing to the Queue Proxy region to ensure atomicity. The length of a burst to add or pop a packet will vary depending on the optional features that the queue supports, which may be 4, 8, 12, or 16 bytes. Queue N Register D must always be written / read in the burst, but the preceding words are optional depending on the required queue functionality.
NOTE
If a program reads or writes Registers A, B, or C in the Queue Management region or writes to the Queue Proxy region without also reading/writing Register D, the hardware assumes an implied read/write to Register D, and the queue will be popped/pushed. This can cause unpredictable results, because either the popped descriptor address will be lost, or an unknown value (or 0) may be pushed. The problem reduces to Registers C and D, because Registers A and B are read-only and should almost always be read from the Queue Peek region.