SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
For accumulation purposes, the firmware will read the queue status RAM to obtain status information on the programmed queues. So the host software must program the Queue N Status and Configuration Register D registers with the value 0x81 for every queue that is to be examined by the firmware. This will cause the status bit in the queue status RAM to be set while the queue is not empty, and clear when empty.
The 32-channel version provides 32 high channels - i.e. channels 0 to 31 that are serviced once per iteration through the channels. The 16-channel firmware provides 16 channels (0...15) that are also scanned as fast as possible (e.g. high), yet these trigger the low priority interrupts. In this way, the 16- and 32-channel accumulators may be used together without interrupt interference. The 48-channel version provides channels 0 to 31 that are high, and channels 32 to 47 that are low — serviced one at a time through each iteration through channels 0 to 31. Note that any channel in any version of the firmware may be configured to monitor 32 contiguous queues, not just the low priority channels.
The accumulator is programmed using a 20-byte shared memory command buffer. The command buffer consists of a command word, followed by several parameters. The process of writing a command is to check to see if the command buffer is free, then write the command parameters, and finally write the command. Optionally, the calling program can wait for command completion.
The command buffer is free when the command field is set to 0x00.
When a command is written, the host CPU must write the word containing the command byte last. The command byte is written with bit 7 set to signify a command to the PDSP. The command buffer is in internal RAM and should not be marked as cacheable by the host CPU. If the RAM is cached on the host CPU, then the host must perform two separate writes and cache flushes; the first for writing the parameters, and then a second independent write and cache flush for writing the command word. All writes should be performed as 32 bit quantities.
Once the command is written, the PDSP will clear the command field upon command completion. The command results can then be read from the return code field. Note that the PDSP must be enabled before the firmware can be programmed.