Many clock inputs are low jitter clock buffers (LJCBs). These input buffers accept LVDS and LVPECL signaling levels but must be AC coupled. The LJCBs do not support DC coupling to these interface standards.
The LJCB input buffers include a 100 Ω parallel termination (P to N) and common mode biasing. Because the common mode biasing is included, the clock source must be AC coupled using a 0.1 µF ceramic capacitor (0402 size or smaller recommended).
There are other clock inputs that are not LJCBs that must be conditioned differently for that specific device as discussed in the device-specific Hardware Design Guide. For the link, see Section 2.
All clock inputs have jitter limitations. SerDes clock inputs have very stringent jitter limitations. For various interfaces on the jitter requirements, see the device-specific Hardware Design Guide. For the link, see Section 2.