SPRABI1D January 2018 – July 2022 66AK2E05 , 66AK2G12 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
As a rule of thumb, terminations should be applied to all clock, address, and control lines. Although all address, control, and command lines should be end-terminated when using leveling, clocking nets may require different termination values than that used on the command and address nets. Each respective address and command net should be end-terminated using a resistor (in the range of 39 Ω to 42 Ω) and connected to VTT (preferred value is 39 Ω, 1%). VTT is defined as VDDq/2 or 0.75 V.
The DDR3 clock nets also must be end-terminated. However, instead of end-terminating the clock nets (DDRCLKOUTP/Nx where x is DDRCLKOUTP/N0 or DDRCLKOUTP/N1, whichever is used), each net should be terminated with a series 39-Ω, 1% resistor to a 0.1-μF capacitor to DVDD15 (VDDq). Figure 3-2 (and respective notes) show the required clock termination implementation. All components should be 1% tolerance or better. VTT should be generated using a resistor divider network (1% tolerance or better). For proper operation, the VTT termination must track VDDq/2.
Again, an important point is that the parallel termination should be placed at the last SDRAM in the fly-by or daisy-chained architecture. Each trace to the respective termination should be ≤ within 500 mils and the opposite side of the termination resistor should tie directly to the VTT rail.
External terminations may not be required – the only way to determine if your topology requires end terminations is to perform complete simulations inclusive of all topology parasitics.