The following rules must be followed when routing address/command nets in a DDR3 design:
- 50-Ω (±5%) single-ended impedance required.
- All nets in the address and command fly-by groups must route along the same path from the controller to each SDRAM sequentially, and then to the VTT termination.
- All nets in the address and command fly-by groups must be length-matched from the controller to each SDRAM separately within ±20 mils of the clock along the same route.
- All nets in the address and command fly-by groups must have the same number of vias in each length-matched segment.
- Address lines cannot be swapped to simplify routing.
- Address and command fly-by groups must have stubs less than 80 mils and be length-matched within ±10 mils.
- All nets in the address and command fly-by groups must route adjacent to a solid ground plane or a solid DVDD15 power plane with adequate distributed decoupling to provide high frequency return.
- All nets in the address and command fly-by groups should be routed on close layers to minimize via skew – these are normally close to the center or upper layers of the board.
Table 6-2 shows the numeric routing rules listed above for address/command lines.
Table 6-2 Address and Command Line Numeric Routing Rules| Rule Number | Parameter | Value | Unit |
|---|
| 1 | Net Impedance (single-ended) | 50 | Ω |
| 2 | Skew between fly-by group nets | ± 20 | mils |
| 3 | Stub length | < 80 | mils |
| 4 | Stub skew | ± 10 | mils |