SNLA437A December 2023 – October 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I
- 1
- Abstract
- Trademarks
- 1DP83822 Application Overview
-
2Troubleshooting the PHY Application
- 2.1 Schematic and Layout Checklist
- 2.2 Device Health Checks
- 2.3 MDI Health Checks
- 2.4 MII Health Checks
- 2.5 Loopback and PRBS
- 3Tools and References
- 4Summary
- 5References
- 6Revision History
2.4.2 RMII Check
The DP83822 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification from the RMII consortium. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. The DP83822 offers two types of RMII operations: RMII Leader and RMII Follower.
In RMII Leader operation, the DP83822 operates off of either a 25MHz CMOS-level oscillator connected to XI pin or a 25MHz crystal connected across XI and XO pins.
In RMII Follower operation, the DP83822 operates off of a 50MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC.
A 50MHz output clock referenced from any of the three GPIOs is connected to the MAC.
The RMII specification has the following characteristics:
- Supports 100BASE-FX, 100BASE-TX and 10BASE-Te.
- Single clock reference sourced from the MAC to PHY (or from an external source)
- Provides independent 2-bit wide transmit and receive data paths
- Uses CMOS signal levels, the same levels as the MII interface
In this mode, data transfers are two bits for every clock cycle using the internal 50MHz reference clock for both transmit and receive paths.
The RMII signals are summarized in Table 2-19.
| Function | Pins |
|---|---|
| Data Signals | TX_D[1:0] |
| RX_D[1:0] | |
| Transmit and Receive Signals | TX_EN |
| CRS_DV |
Figure 2-16 RMII Follower Signaling
Figure 2-17 RMII Leader Signaling| TEST CONDITION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| XI Clock Period | 20 | ns | ||
| TX_D[1:0] and TX_EN Data Setup to XI rising | 1.4 | ns | ||
| TX_D[1:0] and TX_EN Data Hold from XI rising | 2 | ns | ||
| RMII Master Clock (RX_D3 Clock) Period | 20 | |||
| Duty Cycle | 35 | 65 | % | |
| TX_D[1:0] and TX_EN Data Setup to RMII Leader Clock rising | 4 | ns | ||
| TX_D[1:0] and TX_EN Data Hold from RMII Leader Clock rising | 2 | ns |
| TEST CONDITION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| XI Clock Period | 20 | ns | ||
| TX_D[1:0] and TX_EN Data Setup to XI rising | 1.4 | ns | ||
| TX_D[1:0] and TX_EN Data Hold from XI rising | 2 | ns | ||
| RMII Master Clock (RX_D3 Clock) Period | 20 | |||
|
Duty Cycle |
35 | 65 | % | |
| TX_D[1:0] and TX_EN Data Setup to RMII Leader Clock rising | 4 | ns | ||
| TX_D[1:0] and TX_EN Data Hold from RMII Leader Clock rising | 2 | ns |
Data on TX_D[1:0] are latched at the PHY with reference to the 50MHz-clock in RMII Leader mode and Follower mode. Data on RX_D[1:0] is provided in reference to 50MHz clock. In addition, CRS_DV can be configured as RX_DV signal. This allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication.
Figure 2-18 RX_CLK and RX_D0 Timing for RMII (Yellow Waveform (Channel 1) = RX_CLK, Blue Waveform (Channel 2) = RX_D0)For more information on reduced media independent interface, see the Reduced Media Independent Interface (RMII) section of the DP83822 Robust, Low Power 10/100 Mbps Ethernet Physical Layer Transceiver Data Sheet.