SNLA437A December 2023 – October 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I
- 1
- Abstract
- Trademarks
- 1DP83822 Application Overview
-
2Troubleshooting the PHY Application
- 2.1 Schematic and Layout Checklist
- 2.2 Device Health Checks
- 2.3 MDI Health Checks
- 2.4 MII Health Checks
- 2.5 Loopback and PRBS
- 3Tools and References
- 4Summary
- 5References
- 6Revision History
2.2.1.1 Power Supply Ramp with Unstable XI Clock
Ensure that the stable XI clock is available at power-up of the PHY. The PHY will not initialize properly if there is no stable XI clock available. If this is not possible, hold the PHY in reset until XI is stabilized after power-up of the PHY. Refer to Table 2-3 and Figure 2-2 for detailed timing requirements and timing diagram if the XI clock is probed to be unstable at power-up of DP83822.
Table 2-3 Timing Requirements: Power-Up
With Unstable XI Clock
| PARAMETER | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|
| T1 | Reset application after XI stabilization | 1 | us | ||
| T2 | Reset pulse width | 10 | us | ||
Figure 2-2 Power-Up With Unstable XI
Input