SNLA437A December 2023 – October 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I
The Media Independent Interface is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC. The MII is fully compliant with IEEE 802.3-2002 clause 22.
The MII signals are summarized in .Table 2-14
| Function | Pins |
|---|---|
| Data Signals | TX_D[3:0] |
| RX_D[3:0] | |
| Transmit and Receive Signals | TX_EN |
| RX_DV | |
| Line-Status Signals | CRS |
| COL | |
| Clock | TX_CLK |
| RX_CLK |
Figure 2-14 MII SignalingReference the waveforms below to verify the expected MAC data and clock signals for 100BASE-Tx MII Mode. Table 2-24 displays specs taken from the data sheet shown in the waveforms. MII signaling needs to be 2.5MHz if PHY is not linked up or linked up at 10Mbps, and needs to be at 25MHz if linked at 100Mbps. Note that both TX_CLK and RX_CLK are outputs of the PHY.
If a MAC bus (TX or RX) is suspected to be problematic, probe the lines at the receiver side of the trace, making sure that the receiver's setup and hold times are met, along with VIH/VIL. Typical symptoms of violating these specifications is packet errors at the MAC while the PHY is indicating clean traffic (Reg 0x15).
| Test Condition | MIN | TYP | MAX | Unit |
|---|---|---|---|---|
| RX_CLK High / Low Time | 16 | 20 | 24 | ns |
| RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising | 10 | 30 | ns |
| TEST CONDITION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| TX_CLK High / Low Time | 16 | 20 | 24 | ns |
| TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK | 10 | ns | ||
| TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK | 0 | ns |
| TEST CONDITION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| RX_CLK High / Low Time | 160 | 200 | 240 | ns |
| RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising | 100 | 300 | ns |
| TEST CONDITION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| TX_CLK High / Low Time | 190 | 200 | 240 | ns |
| TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK | 25 | ns | ||
| TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK | 0 | ns |