If generating and checking packets with the MAC is not possible, use an external packet generator or internal PRBS packet generation and check functionalities to verify the data path. Perform reverse loopback with PRBS and a working link partner as follows:

1. Power and connect the PHY to a link partner.
2. Enable PRBS packet generation on the PHY (write 0x16 to 5000).
3. Enable reverse loopback on the link partner
4. Wait at least one second, then check PRBS lock status on the PHY (read register 0x17[11:10]).

If register 0x17[11] is high, the data path through PHY → MDI is valid. If this test does not pass, the issue could be on the PHY's internal data path or the MDI. To verify the internal data path, perform PRBS with analog loopback using the following script. If the internal data path is valid, then the issue is isolated to the MDI (assuming the link partner is working).

The following code are example sequences of register reads and writes to perform BIST when using two DP83822 PHY's:

// Reverse Loopback on PHY

begin

001F 8000 //Hard Reset
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 7100 //Enables PRBS packet generation
0016 // check PRBS lock status on bit 10 high

end

// Reverse Loopback on Link Partner

begin

001F 8000 //Hard Reset
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0110 //Select Reverse Loopback

end