ZHCSRQ4 august 2023 TPSM8S6C24
PRODUCTION DATA
| CMD Address | 60h |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | SLINEAR11 per CAPABILITY |
| Phased: | No |
| NVM Back-up: | EEPROM |
| Updates: | On-the-fly |
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received (as programmed by the ON_OFF_CONFIG command) until the output voltage starts to rise.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| TONDLY_EXP | TONDLY_MAN | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| TONDLY_MAN | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:11 | TONDLY_ EXP | RW | 11111b | Linear format two’s complement exponent. |
| 10:0 | TONDLY_ MAN | RW | NVM | Linear format two’s complement mantissa. Note, a minimum turn-on delay of approximately 100 μs is observed even when TON_DELAY during which the device initializes itself at every power-on. |
Attempts to write (60h) TON_DELAY beyond the supported range will be considered invalid/unsupported data and cause the TPSM8S6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3. TON_DELAY supports values from 0ms to 127.5 ms in 0.5-ms steps. Following a Power Cycle or STORE/RESTORE, TON_DELAY will be restored to the nearest supported value.
Refer to the Start-Up and Shutdown behavior section for handling of corner cases with respect to interrupted TON_DELAY, TON_RISE , TOFF_FALL, and TOFF_DELAY times.