ZHCSRQ4 august 2023 TPSM8S6C24
PRODUCTION DATA
Using Equation 19, the maximum input RMS current is 14.95A and the input capacitors must be rated to handle this. When calculating this, the maximum output current must be divided by the number of phases. The output current is divided by the number of phases because the switching nodes are interleaved. Interleaving the switching node effectively divides the amplitude of the current pulses the input capacitor by the number of phases. With the 16-V maximum input in this example, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage.
For this design, allow 0.1-V input ripple for VRIPPLE(cap) and 0.2-V input ripple for VRIPPLE(esr). Using Equation 20 and Equation 21, the minimum input capacitance for this design is 2 x 40.4 μF and the maximum ESR is half of 5.15 mΩ, respectively. Again, the maximum output current must be divided by the number of phases and the calculated capacitance must be placed near the loop controller device and all of the loop follower devices. 8 x 22-μF, 25-V ceramic capacitors and 4 x 6800-pF, 25-V ceramic capacitors in parallel were selected to bypass the power stage with sufficient margin. Additionally, 2 x 100-μF, 25-V low-ESR electrolytic capacitors were placed on the input to minimize deviations on the input during transients. These capacitors are distributed equally between the phases. To minimize the high frequency ringing, the high frequency 6800-pF PVIN bypass capacitors must be placed close to power stage.
When stacking converters the amount of input RMS current and the amount if input capacitance required can be further reduced. The amount of ripple cancellation depends on the number of phases and the duty cycle. PCB inductance between the phases can also reduce the effects of ripple cancellation. The calculations given in this example ignore the effects of ripple cancellation.