11 Revision History
Changes from Revision F (April 2019) to Revision G (May 2024)
- 在說明 部分中添加了指向其他 TI 器件的超鏈接和有關 DLP 投影儀資源的附加信息Go
- 將整個出版物中多個位置的 DMD 和控制器參考進行了歸納,以包括 TPS99000-Q1 系統管理控制器的所有可能組合。Go
- Added LS_SENSE_P and LS_SENSE_N to Absolute Maximum TableGo
- Added AVDD, DVDD and VDDIO trip threshold voltageGo
- Footnote (3) and (4) added to Power-Up Timing Requirements Table explaining how to account for
each internal TPS monitor test prior to RESETZ being
de-asserted.Go
- Swapped pin 76 and 77 in the Illumination Control Loop
figureGo
- Swapped pin 76 and 77 in the Continuous Mode Signal Example
figureGo
- Swapped pin 76 and 77 in Blanking Current
Paths
Go
- Swapped pin 76 and 77 in
Figure 6-14
Go
- Swapped pin 76 and 77 in Current Limit Configuration
Circuit
Go
Changes from Revision E (June 2018) to Revision F (April 2019)
- Deleted TYP VSAT because it is not applicable given VOUTDAC MAX
Go
- Deleted TSLEW because it is redundant given TSET
Go
- Added footnote regarding capacitor characteristics for voltage regulatorsGo
Changes from Revision D (May 2018) to Revision E (June 2018)