ZHCSIF5G December 2015 – July 2024 TPS99000-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics—Transimpedance Amplifier Parameters
- 5.6 Electrical Characteristics—Digital to Analog Converters
- 5.7 Electrical Characteristics—Analog to Digital Converter
- 5.8 Electrical Characteristics—FET Gate Drivers
- 5.9 Electrical Characteristics—Photo Comparator
- 5.10 Electrical Characteristics—Voltage Regulators
- 5.11 Electrical Characteristics—Temperature and Voltage Monitors
- 5.12 Electrical Characteristics—Current Consumption
- 5.13 Power-Up Timing Requirements
- 5.14 Power-Down Timing Requirements
- 5.15 Timing Requirements—Sequencer Clock
- 5.16 Timing Requirements—Host and Diagnostic Port SPI Interface
- 5.17 Timing Requirements—ADC Interface
- 5.18 Switching Characteristics
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1
Illumination Control
- 6.3.1.1 Illumination System High Dynamic Range Dimming Overview
- 6.3.1.2 Illumination Control Loop
- 6.3.1.3 Continuous Mode Operation
- 6.3.1.4
Discontinuous Mode Operation
- 6.3.1.4.1 Discontinuous Mode Pulse Width Limit
- 6.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
- 6.3.1.4.3 Dimming Within Discontinuous Operation Range
- 6.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
- 6.3.1.4.5 TIA Gain Adjustment
- 6.3.1.4.6 Current Limit in Discontinuous Mode
- 6.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
- 6.3.2 Over-Brightness Detection
- 6.3.3 Analog to Digital Converter
- 6.3.4 Power Sequencing and Monitoring
- 6.3.5 DMD Mirror Voltage Regulator
- 6.3.6 Low Dropout Regulators
- 6.3.7 System Monitoring Features
- 6.3.8 Communication Ports
- 6.3.1
Illumination Control
- 6.4 Device Functional Modes
- 6.5 Register Maps
- 7 Application and Implementation
- 8 Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
- PZP|100
散熱焊盤機械數據 (封裝 | 引腳)
- PZP|100
訂購信息
5.13 Power-Up Timing Requirements
| TYP | UNIT | |||
|---|---|---|---|---|
| ten_dly | PROJ_ON to 1.1V enable. This includes PROJ_ON tglitch time. | Rising edge of PROJ_ON to rising edge of 1.1V enable | 11 | ms |
| tmon1(1)(2) | Maximum time for 1.1V rail to reach voltage threshold after enable has been asserted. This delay length will occur even if 1.1V meets threshold earlier. | Rising edge of ENB_1P1V to internal 1.1V monitor test (3) | 10 | ms |
| tmon2(1)(2) | Maximum time for 1.8V rail to reach voltage threshold after enable has been asserted. This delay length will occur even if 1.8V meets threshold earlier. | Rising edge of ENB_1P8V to internal 1.8V monitor test (3) | 10 | ms |
| tmon3(1)(2) | Maximum time for 3.3V rail to reach voltage threshold after enable has been asserted. This delay length will occur even if 3.3V meets threshold earlier. | Rising edge of ENB_3P3V to internal 3.3V monitor test (3) | 10 | ms |
| tw1(4) | RESETZ delay after voltage testing completion. | Completion of 3.3V monitor test to RESETZ rising edge | 10 | ms |
(1) V1P1V, V1P8V, and V3P3V rails may be enabled prior to the TPS99000-Q1
assertion of their respective enable signal if required for system power design.
If necessary, ENB_1P1V may be connected to the 1.1V, 1.8V, and 3.3V external
supply enables.
(2) If any voltage threshold is not met within the specified time,
the TPS99000-Q1
will not deassert RESETZ. The power-up procedure must be fully restarted in this
situation.
(3) Each TPS monitor test is
performed approximately 10 ms from the voltage rail’s respective voltage enable.
The voltage rail may come to its threshold value any time before this. This
means there should be approximately 10 ms between each enable. The time for the
respective 1.1V, 1.8V, and 3.3V to come up will differ by design and parts
chosen, but they must all be valid before the monitor test.
(4) tw1 starts after the
3.3V rail passes its internal monitor tests (~10 ms). This time does not start
as soon as the 3.3V comes to its threshold value. This time starts after the
internal TPS monitor check for 3.3V passes. After the test passes, there will be
a 10 ms delay before RESETZ may be de-asserted. This means there will be
approximately 20 ms delay from the time the 3.3V enable is valid to the time
RESETZ is de-asserted.
Figure 5-1 Power Up
Timing