ZHCSIF5G December 2015 – July 2024 TPS99000-Q1
PRODUCTION DATA
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 6 | WD1 | I | Watchdog interrupt channel 1 |
| 7 | WD2 | I | Watchdog interrupt channel 2 |
| 8 | PARK_Z | O | DMD mirror parking signal (active low) |
| 9 | RESET_Z | O | Reset output to the DLPC23x-Q1. TPS99000-Q1 controlled. |
| 10 | INT_Z | O | Interrupt output signal to DLPC23x-Q1 (open drain). Recommended to pull up to the DLPC23x-Q1 3.3V rail controlled by the TPS99000-Q1's ENB_3P3V signal. |
| 11 | PROJ_ON | I | Input signal to enable/disable the IC and DLP projector |
| 16 | SEQ_START | I | PWM shadow latch control; indicates a start of sequence |
| 17 | SEQ_CLK | I | Sequencer clock |
| 40 | DMUX0 | O | Digital test point output |
| 41 | DMUX1 | O | Digital test point output |
| 57 | AMUX1 | O | Analog test mux output 1 |
| 61 | AMUX0 | O | Analog test mux output 0 |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 13, 35 | VSS_IO | GND | Ground connection for digital IO interface |
| 14, 36 | VDD_IO | POWER | 3.3V power input for IO rail supply |
| 24 | DVSS | GND | Digital core ground return |
| 25, 60, 75, 99 | PBKG | GND | Substrate tie and ESD ground return |
| 26 | DVDD | POWER | 3.3V power input for digital core supply |
| 42 | DRVR_PWR | POWER | 6V or 3.3V power input for FET driver power. Supply for S_EN1, S_EN2, R_EN, G_EN, and B_EN outputs |
| 48 | VSS_DRVR | GND | Ground connection for FET driver power |
| 49 | DMD_VOFFSET | POWER | VOFFSET output rail. Connect a 1μF ceramic capacitor to ground |
| 50 | DMD_VBIAS | POWER | VBIAS output rail. Connect a 0.47μF ceramic capacitor to ground |
| 51 | DMD_VRESET | POWER | VRESET output rail. Connect a 1μF ceramic capacitor to ground. Connect to DRST_HS_IND through external diode. Connect anode of diode to DMD_VRESET. |
| 53 | DRST_PGND | GND | Power ground for DMD power supply. Connect to ground plane |
| 55 | VIN_DRST | POWER | 6V input for DMD power supply |
| 56 | VSS_DRST | GND | Ground supply for DMD power supply |
| 59 | AVDD | POWER | 3.3V power supply input for analog circuit |
| 63 | VLDOT_M8 | POWER | Dedicated TIA interface –8V LDO output |
| 64 | VLDOT_5V | POWER | Filter cap interface for 5V TIA LDO |
| 65 | VIN_LDOT_5V | POWER | 6V power input for 5V TIA LDO |
| 66 | GND_LDO | GND | Power ground return for LDO |
| 67 | VIN_LDOT_3P3V | POWER | 6V power input for 3.3V TIA LDO |
| 68 | VLDOT_3P3V | POWER | Filter cap interface for 3.3V TIA LDO |
| 71 | VSS_TIA2 | GND | TIA2 Dedicated Ground |
| 72 | VSS_TIA1 | GND | TIA1 dedicated ground |
| 78, 100 | AVSS | GND | Analog ground |
| 79 | VIN_LDOA_3P3 | POWER | 6V power input for dedicated ADC interface 3.3V LDO supply |
| 80 | VLDOA_3P3 | POWER | Dedicated ADC interface 3.3V LDO filter cap output |
| 81, 84, 87, 89, 91 | VSSL_ADC | GND | External ADC channel bondwire and lead frame isolation ground |
| 95 | ADC_VREF | POWER | ADC reference voltage output |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | ENB_1P1V | O | External 1.1V buck enable. 3.3V output |
| 2 | ENB_1P8V | O | External 1.8V buck enable. 3.3V output |
| 3 | ENB_3P3V | O | External 3.3V buck enable. 3.3V output |
| 52 | DRST_LS_IND | ANA | Connection for the DMD power supply inductor (10μH). Connect a 330pF, 50V capacitor to ground. X7R recommended |
| 54 | DRST_HS_IND | ANA | Connection for the DMD power supply inductor (10μH) |
| 58 | VMAIN | I | Main intermediate voltage monitor input. Use an external resistor divider to set voltage input for brownout monitoring. |
| 62 | VIN_LDOT_M8 | O | Dedicated TIA interface –8V LDO external regulation FET drive signal |
| 96 | V3P3V | I | External 3.3V buck voltage monitor input |
| 97 | V1P8V | I | External 1.8V buck voltage monitor input |
| 98 | V1P1V | I | External 1.1V buck voltage monitor input |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 12 | COMPOUT | O | Photodiode (PD) interface high-speed comparator output |
| 15 | SYNC | O | External LED buck driver sync strobe output |
| 18 | D_EN | I | LED interface; buck high-side FET drive enable |
| 19 | S_EN | I | LED bypass shunt strobe input |
| 20 | LED_SEL_0 | I | LED enable strobe 0 input |
| 21 | LED_SEL_1 | I | LED enable strobe 1 input |
| 22 | LED_SEL_2 | I | LED enable strobe 2 input |
| 23 | LED_SEL_3 | I | LED enable strobe 3 input |
| 37 | EXT_SMPL | I | Reserved. Connect to ground |
| 38 | DRV_EN | O | Drive enable for LM3409 |
| 39 | CMODE | O | Capacitor selection output (allows for a smaller capacitance to be used in CM mode for less overshoot or undershoot). Open drain. |
| 43 | S_EN1 | O | Low resistance shunt NFET drive enable [high means shunt active] |
| 44 | S_EN2 | O | High resistance shunt NFET drive enable [high means shunt active] |
| 45 | R_EN | O | Red channel select. Drive for low side NFET. |
| 46 | G_EN | O | Green channel select. Drive for low side NFET. |
| 47 | B_EN | O | Blue channel select. Drive for low side NFET. |
| 69 | TIA_PD2_FILT | O | TIA2 external filter cap - low bandwidth sampling |
| 70 | TIA_PD2 | I | TIA2 photodiode cathode driver |
| 73 | TIA_PD1 | I | TIA1 photodiode cathode driver |
| 74 | TIA_PD1_FILT | O | TIA1 external filter cap - low bandwidth sampling |
| 76 | R_IADJ | ANA | External resistance for IADJ voltage to current transformation |
| 77 | IADJ | ANA | Current output used to adjust external LED controller drive current set point |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 27 | SPI1_CLK | I | SPI control interface (DLPC23x-Q1 primary, TPS99000-Q1 secondary), clock input |
| 28 | SPI1_SS_Z | I | SPI control interface (DLPC23x-Q1 primary, TPS99000-Q1 secondary), chip select (active low) |
| 29 | SPI1_DOUT | O | SPI control interface (DLPC23x-Q1 primary, TPS99000-Q1 secondary), transmit data output |
| 30 | SPI1_DIN | I | SPI control interface (DLPC23x-Q1 primary, TPS99000-Q1 secondary), receive data input |
| 31 | SPI2_DIN | I | SPI diagnostic port (secondary), receive data input. For read-only monitoring |
| 32 | SPI2_DOUT | O | SPI diagnostic port (secondary), transmit data output. For read-only monitoring |
| 33 | SPI2_SS_Z | I | SPI diagnostic port (secondary), chip select (active low). For read-only monitoring |
| 34 | SPI2_CLK | I | SPI diagnostic port (secondary), clock input. For read-only monitoring |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 4 | ADC_MISO | O | ADC 2-wire interface - data output. DLPC23x-Q1 primary, TPS99000-Q1 secondary. |
| 5 | ADC_MOSI | I | ADC 2-wire interface - data input. DLPC23x-Q1 primary, TPS99000-Q1 secondary. |
| 82 | LS_SENSE_N | I | Low side current sense ADC negative input, see Table 6-2 |
| 83 | LS_SENSE_P | I | Low side current sense ADC positive input, see Table 6-2 |
| 85 | ADC_IN1 | I | External ADC channel 1, see Table 6-2 |
| 86 | ADC_IN2 | I | External ADC channel 2, see Table 6-2 |
| 88 | ADC_IN3 | I | External ADC channel 3, see Table 6-2 |
| 90 | ADC_IN4 | I | External ADC channel 4, see Table 6-2 |
| 92 | ADC_IN5 | I | External ADC channel 5, see Table 6-2 |
| 93 | ADC_IN6 | I | External ADC channel 6, see Table 6-2 |
| 94 | ADC_IN7 | I | External ADC channel 7, see Table 6-2 |