ZHCSIF5G December 2015 – July 2024 TPS99000-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics—Transimpedance Amplifier Parameters
- 5.6 Electrical Characteristics—Digital to Analog Converters
- 5.7 Electrical Characteristics—Analog to Digital Converter
- 5.8 Electrical Characteristics—FET Gate Drivers
- 5.9 Electrical Characteristics—Photo Comparator
- 5.10 Electrical Characteristics—Voltage Regulators
- 5.11 Electrical Characteristics—Temperature and Voltage Monitors
- 5.12 Electrical Characteristics—Current Consumption
- 5.13 Power-Up Timing Requirements
- 5.14 Power-Down Timing Requirements
- 5.15 Timing Requirements—Sequencer Clock
- 5.16 Timing Requirements—Host and Diagnostic Port SPI Interface
- 5.17 Timing Requirements—ADC Interface
- 5.18 Switching Characteristics
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1
Illumination Control
- 6.3.1.1 Illumination System High Dynamic Range Dimming Overview
- 6.3.1.2 Illumination Control Loop
- 6.3.1.3 Continuous Mode Operation
- 6.3.1.4
Discontinuous Mode Operation
- 6.3.1.4.1 Discontinuous Mode Pulse Width Limit
- 6.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
- 6.3.1.4.3 Dimming Within Discontinuous Operation Range
- 6.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
- 6.3.1.4.5 TIA Gain Adjustment
- 6.3.1.4.6 Current Limit in Discontinuous Mode
- 6.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
- 6.3.2 Over-Brightness Detection
- 6.3.3 Analog to Digital Converter
- 6.3.4 Power Sequencing and Monitoring
- 6.3.5 DMD Mirror Voltage Regulator
- 6.3.6 Low Dropout Regulators
- 6.3.7 System Monitoring Features
- 6.3.8 Communication Ports
- 6.3.1
Illumination Control
- 6.4 Device Functional Modes
- 6.5 Register Maps
- 7 Application and Implementation
- 8 Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PZP|100
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PZP|100
訂購信息
6.3.1.3.5 Continuous Mode Current Limit
In continuous mode, a current limit feature prevents damage to LEDs if the requested light output cannot be achieved within LED current specifications. This could happen due to high temperature, or when an LED ages and requires more current to achieve the same brightness. Systems should be designed with sufficient thermal and LED lifetime margin that this would not happen in practice.
The control scheme utilizes the built-in current limit feature of the LM3409 device plus a 10-bit DAC-based adjustment feature included in the TPS99000-Q1. This serves as an alternate limit for the current for the LEDs—the inductor drive will be disabled if either the current limit is met or if the photo feedback limit is met, whichever is lower. This peak current limit is configurable on a per LED basis and is in use during the light-on active periods only. (During blanking periods, this same structure is used to control the blanking current, but different values are loaded onto the ILIM DAC).
The schematic for the current adjustment mechanism is shown in Figure 6-14.
Figure 6-14 IADJ Peak
Current Limit SchematicBy design, the LM3409 seeks to create a zero voltage difference between the CSP and CSN pins when the IADJ pin is held low and the system is operating in peak current limit mode. If the CSP pin voltage is higher than the CSN pin voltage, the PGATE driver is held high (PFET off).
When the ILIM DAC is set to a non-zero voltage, a current is established on the IADJ line of the TPS99000-Q1 device, which pulls the voltage of the CSP pin downward. If the LM3409 device is enabled and PFET drive is not held off by the state of the COFF pin, then the current will go up until the voltage across the sense resistor is such that the CSN pin is equal to or greater than the voltage on the CSP pin, at which point the PFET is turned off.
Care must be taken with the routing of the IADJ pin of the TPS99000-Q1 to ensure that it is well isolated from noisy switching nodes, such as the PFET drain node.