ZHCSG47D February 2017 – June 2025 TPS7B63-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Device Enable (EN)
- 6.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
- 6.3.3 Adjustable Power-Good Delay Timer (DELAY)
- 6.3.4 Undervoltage Shutdown
- 6.3.5 Current Limit
- 6.3.6 Thermal Shutdown
- 6.3.7
Integrated Watchdog
- 6.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)
- 6.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)
- 6.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)
- 6.3.7.4 ROSC Status Detection (ROSC)
- 6.3.7.5 Watchdog Enable (PG and WD_EN)
- 6.3.7.6 Watchdog Initialization
- 6.3.7.7 Window Watchdog Operation (WTS = Low)
- 6.3.7.8 Standard Watchdog Operation (WTS = High)
- 6.4 Device Functional Modes
- 7 Application and Implementation
- 8 器件和文檔支持
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
6.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
The PG pin is an open-drain output with an external pullup resistor to the regulated supply, and the PGADJ pin is a power-good threshold adjustment pin. Connecting the PGADJ pin to GND sets the power-good threshold value to the default, V(PG_TH). When VOUT exceeds the default power-good threshold, the PG output turns high after the power-good delay period has expired. When VOUT falls below V(PG_TH) – V(PG_HYST), the PG output turns low after a short deglitch time.
The power-good threshold is also adjustable from 1.1 V to 5 V by using an external resistor divider between PGADJ and OUT. The threshold can be calculated using Equation 1:
where
- V(PG_ADJ) is the adjustable power-good threshold
- V(PG_REF) is the internal comparator reference voltage of the PGADJ pin, 1.1 V typical, 2% accuracy specified under all conditions
By setting the power-good threshold V(PG_ADJ), when VOUT exceeds this threshold, the PG output turns high after the power-good delay period has expired. When VOUT falls below V(PG_ADJ) – V(PG_HYST), the PG output turns low after a short deglitch time. Figure 6-1 shows typical hardware connections for the PGADJ pin and DELAY pin.
Figure 6-1 Adjustable Power-Good
Threshold