ZHCSG47D February 2017 – June 2025 TPS7B63-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Device Enable (EN)
- 6.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
- 6.3.3 Adjustable Power-Good Delay Timer (DELAY)
- 6.3.4 Undervoltage Shutdown
- 6.3.5 Current Limit
- 6.3.6 Thermal Shutdown
- 6.3.7
Integrated Watchdog
- 6.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)
- 6.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)
- 6.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)
- 6.3.7.4 ROSC Status Detection (ROSC)
- 6.3.7.5 Watchdog Enable (PG and WD_EN)
- 6.3.7.6 Watchdog Initialization
- 6.3.7.7 Window Watchdog Operation (WTS = Low)
- 6.3.7.8 Standard Watchdog Operation (WTS = High)
- 6.4 Device Functional Modes
- 7 Application and Implementation
- 8 器件和文檔支持
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
6.3.3 Adjustable Power-Good Delay Timer (DELAY)
The power-good delay period is a function of the value set by an external capacitor on the DELAY pin before turning the PG pin high. Figure 6-2 illustrates typical power-good and delay behavior. Connecting an external capacitor from this pin to GND sets the power-good delay period. The constant current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator, and Equation 2 determines the power-good delay period:
Equation 2. 
where
- t(DLY) is the adjustable power-good delay period
- CDELAY is the value of the power-good delay capacitor
Figure 6-2 Power Up and Conditions for
Activating Power-GoodIf the DELAY pin is open, the default delay time is t(DLY_FIX).