ZHCSG47D February 2017 – June 2025 TPS7B63-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER-GOOD DELAY (DELAY) | ||||||
| t(DEGLITCH) | Power-good deglitch time | 50 | 180 | 250 | μs | |
| t(DLY_FIX) | Fixed power-good delay | No capacitor connect at DELAY pin | 248 | 900 | μs | |
| t(DLY) | Power-on-reset delay | Delay capacitor value: C(DELAY) = 100 nF | 20 | ms | ||
| WATCHDOG (WD, WDO, WRS) | ||||||
| t(WD) | Watchdog window duration | R(ROSC) = 20 kΩ ±1%, FSEL = LOW | 9 | 10 | 11 | ms |
| R(ROSC) = 20 kΩ ±1%, FSEL = HIGH | 45 | 50 | 55 | |||
| t(WD_TOL) | Tolerance of watchdog window duration using external resistor | Excludes tolerance of R(ROSC) = 20 kΩ to 100 kΩ | –10% | 10% | ||
| tp(WD) | Watchdog service-signal duration | 100 | μs | |||
| t(WD_HOLD) | Watchdog output resetting time (percentage of settled watchdog window duration) | 20 | % of t(WD) | |||
| t(WD_RESET) | Watchdog output resetting time | R(ROSC) = 20 kΩ ± 1%, FSEL = LOW | 1.8 | 2 | 2.2 | ms |
| R(ROSC) = 20 kΩ ± 1%, FSEL = HIGH | 9 | 10 | 11 | |||