ZHCSG52B March 2017 – May 2018 TPS543C20
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Soft-Start Operation
- 8.4.2 Input and VDD Undervoltage Lockout (UVLO) Protection
- 8.4.3 Power Good and Enable
- 8.4.4 Voltage Reference
- 8.4.5 Prebiased Output Start-up
- 8.4.6 Internal Ramp Generator
- 8.4.7 Switching Frequency
- 8.4.8 Clock Sync Point Selection
- 8.4.9 Synchronization and Stackable Configuration
- 8.4.10 Dual-Phase Stackable Configurations
- 8.4.11 Operation Mode
- 8.4.12 API/BODY Brake
- 8.4.13 Sense and Overcurrent Protection
- 8.4.14 Output Overvoltage and Undervoltage Protection
- 8.4.15 Overtemperature Protection
- 8.4.16 RSP/RSN Remote Sense Function
- 8.4.17 Current Sharing
- 8.4.18 Loss of Synchronization
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application: TPS543C20 Stand-alone Device
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.3 Application Curves
- 9.3 System Example
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVF|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVF|40
訂購信息
9.2.2.4 Input Capacitor Selection
The TPS543C20 devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a value of at least 1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple to the device during full load. The input ripple current can be calculated using Equation 6.
The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are shown in Equation 7 and Equation 8. The input ripple is composed of a capacitive portion, VRIPPLE(cap), and a resistive portion, VRIPPLE(esr).
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input ripple for VRIPPLE(cap), and 0.3-V input ripple for VRIPPLE(esr). Using Equation 7 and Equation 8, the minimum input capacitance for this design is 38.5 µF, and the maximum ESR is 9.4 mΩ. For this example, four 22-μF, 25-V ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for the power stage.