ZHCSG52B March 2017 – May 2018 TPS543C20
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Soft-Start Operation
- 8.4.2 Input and VDD Undervoltage Lockout (UVLO) Protection
- 8.4.3 Power Good and Enable
- 8.4.4 Voltage Reference
- 8.4.5 Prebiased Output Start-up
- 8.4.6 Internal Ramp Generator
- 8.4.7 Switching Frequency
- 8.4.8 Clock Sync Point Selection
- 8.4.9 Synchronization and Stackable Configuration
- 8.4.10 Dual-Phase Stackable Configurations
- 8.4.11 Operation Mode
- 8.4.12 API/BODY Brake
- 8.4.13 Sense and Overcurrent Protection
- 8.4.14 Output Overvoltage and Undervoltage Protection
- 8.4.15 Overtemperature Protection
- 8.4.16 RSP/RSN Remote Sense Function
- 8.4.17 Current Sharing
- 8.4.18 Loss of Synchronization
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application: TPS543C20 Stand-alone Device
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.3 Application Curves
- 9.3 System Example
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.4.10.2 Configuration 2: Master and Slave Sync to External System Clock
- Direct connection between external clock and SYNC pin of Master and Slave.
- Direct VSHARE and ISHARE connections between Master and Slave.
- SYNC pin of master will be configured as sync in by it’s MODE pin.
- Master and Slave receive external system clock from SYNC pin. Their RT pin determine the sync point for clock phase shift.
Figure 19. 2-Phase Stackable with 180° Phase Shift: Master and Slave Sync to External System Clock