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ZHCSG52B March 2017 – May 2018 TPS543C20

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RVF|40
- MPQF268C

散熱焊盤機械數據 (封裝 | 引腳)

RVF|40
- QFND333E

訂購信息

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
MOSFET R_DS(ON)
R_DS(on)HS	HS FET	VBST – VSW = 5 V, I_D = 20 A, T_j= 25°C			3.0		mΩ
R_DS(on)LS	LS FET	VDD = 5 V, I_D = 20 A, T_j= 25°C			0.9		mΩ
t_DEAD(LtoH)	Power stage driver dead-time from Low-side off to High-side on⁽¹⁾	VDD ≥ 12 V, T_J= 25°C			12		ns
t_DEAD(HtoL)	Power stage driver dead-time from High-side off to Low-side on⁽¹⁾	VDDN ≥ 12 V, T_J= 25°C			15		ns
INPUT SUPPLY and CURRENT
V_VIN	Power stage voltage			4		14
V_VDD	VDD supply voltage			4		16
I_VDD	VDD bias current	T_A = 25°C, no load, power conversion enabled (no switching)			4.3		mA
I_VDDSTBY	VDD standby current	T_A = 25°C, no load, power conversion disabled			4.3		mA
UNDERVOLTAGE LOCKOUT
V_{VDD_UVLO}	VDD UVLO rising threshold				3.8		V
V_{VDD_UVLO_HYS}	VDD UVLO hysteresis				0.2		v
V_{VIN_UVLO}	VIN UVLO rising threshold				3.2		V
V_{VIN_UVLO_HYS}	VIN UVLO hysteresis				0.2		v
V_{EN_ON_TH}	EN on threshold			1.45	1.6	1.75	V
V_HYS	EN hysteresis			270	300	330	mV
I_{EN_LKG}	EN input leakage current			–1	0	1	µA
INTERNAL REFERENCE VOLTAGE
V_INTREF	Internal REF voltage	R_VSEL = OPEN			1000		mV
V_INTREFTOL	Internal REF voltage tolerance	T_J = -40°C to 125°C		–0.5%		+0.5%
V_{INTREF_VSEL}	Internal REF voltage range	Programable by VSEL (pin 36)		0.6		1.1	V
OUTPUT VOLTAGE
I_RSP	RSP input current	V_RSP= 600 mV		–1		1	µA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
f_UGBW	Unity gain bandwidth⁽¹⁾			5	8.5		MHz
A0	Open loop gain⁽¹⁾			75			dB
SR	SLew rate⁽¹⁾				±10		V/µs
V_ICM	Input common mode range⁽¹⁾			–0.2		1.7	V
V_OFFSET	Input offset voltage⁽¹⁾	V_RSN-VGND = 0 mV		–1		1	mV
V_OFFSET	Input offset voltage⁽¹⁾	V_RSN-VGND = ±100 mV		–1.9		1.9	mV
SWITCHING FREQUENCY
F_SW	V_O switching frequency maximum frequency for multi-phase is 1MHz	V_IN = 12 V, V_VO= 1 V, RT = 66.5 kΩ			300		kHz
		V_IN = 12 V, V_VO = 1 V, RT = 48.7 kΩ			400
		V_IN = 12 V, V_VO = 1 V, RT = 39.2 kΩ			500
		V_IN = 12 V, V_VO= 1 V, RT = 28.0 kΩ			700
		V_IN = 12 V, V_VO= 1 V, RT = 22.6 kΩ			850
		V_IN = 12 V, V_VO = 1 V, RT = 19.1 kΩ			1000
		V_IN = 12 V, V_VO = 1 V, RT = 15.4 kΩ			1200
		V_IN = 12 V, V_VO = 1 V, RT = 8.06 kΩ			2000
t_ON(min)	Minimum on-time⁽¹⁾	DRVH rising to falling			30		ns
t_OFF(min)	Minimum off-time⁽¹⁾	DRVH falling to rising			250		ns
INTERNAL BOOTSTRAP SWITCH
V_F	Forward voltage	V_BP-VBST, T_A= 25°C, I_F= 5 mA			0.1	0.2	V
VSEL
VSEL	Internal reference voltage	R_VSEL= 0 kΩ			0.6		V
		R_VSEL= 8.66 kΩ			0.7
		R_VSEL= 15.4 kΩ			0.75
		R_VSEL= 23.7 kΩ			0.8
		R_VSEL= 34.8 kΩ			0.85
		R_VSEL= 51.1 kΩ			0.9
		R_VSEL= 78.7 kΩ			0.95
		R_VSEL= OPEN			1
		R_VSEL= 121 kΩ			1.05
		R_VSEL= 187 kΩ			1.1
SOFT START
t_SS	Soft-start time	V_O rising from 0 V to 95% of final set point	R_SS = 0 kΩ		0.5		ms
			R_SS = 8.66 kΩ		1
			R_SS = 15.4 kΩ		2
			R_SS = Open		4
			R_SS = 23.7 kΩ		5
			R_SS = 34.8 kΩ		8
			R_SS = 51.1 kΩ		12
			R_SS = 78.7 kΩ		16
			R_SS = 121 kΩ		24
			R_SS = 187 kΩ		32
POWER ON DELAY
t_PODLY	Power-on delay time	Delay from enable to switching			512		µs
PGOOD COMPARATOR
V_PG(thresh)	OV warning threshold on RSP pin, PGOOD fault threshold on rising	VREF = 600 mV		108	112	116	%V_REF
V_PG(thresh)	UV warning threshold on RSP pin, PGOOD fault threshold on falling	VREF = 600 mV		84	88	92	%V_REF
V_PGD(rise)	PGOOD threshold on rising and UV warning threshold de-assertion threshold at RSP pin	VREF = 600 mV			95		%V_REF
V_PGD(fall)	PGOOD threshold on falling and OV warning threshold de-assertion threshold at RSP pin	VREF = 600 mV			105		%V_REF
R_PGD	PGOOD pulldown resistance	I_PGOOD = 5 mA, VRSP = 0 V		30	45	60	Ω
t_PGDLY	PGOOD delay time	Delay for PGOOD going in			1.024		ms
t_PGDLY	PGOOD delay time	Delay for PGOOD coming out				2	µs
V_PGD(OL)	PGOOD output low level voltage at no supply voltage	VDD=0, I_PGOOD = 80 µA				0.8	V
I_PGLK	PGOOD leakage current	V_PGOOD = 5 V				15	µA
CURRENT SHARE ACCURACY
I_SHARE(acc)	Output current sharing accuracy among stackable devices, defined as the ratio of the current difference between devices to total current(sensing error only)⁽¹⁾	I_OUT ≥ 20 A/phase		–15%		15%
I_SHARE(acc)		I_OUT ≤ 20 A/phase			±3		A
CURRENT DETECTION
V_ILIM	V_TRIP voltage range	R_dson sensing		0.1		1.2	V
I_OCP	Low-side FET current protection threshold and tolerance	R_ILIM= 33.2 kΩ			35		A
I_OCP	Low-side FET current protection threshold and tolerance	OC tolerance			±10%
I_OCP	Low-Side FET Current protection threshold and tolerance	R_ILIM= 23.7 kΩ			25		A
I_OCP	Low-Side FET Current protection threshold and tolerance	OC tolerance			±15%
I_{OCP_N}	Negative current limit threshold	Valley-point current sense			–23		A
I_{CLMP_LO}	Clamp current at V_TRIP clamp at lowest	25°C, V_TRIP = 0.1 V		5.5	6.5	7.5	A
HIGH-SIDE SHORT-CIRCUIT PROTECTION
I_HSOC	High-side short circuit protection fault threshold⁽¹⁾				60		A
OV / UV PROTECTION
V_OVP	OVP threshold voltage	OVP detect voltage		113	117	121	%VREF
t_OVPDLY	OVP response time⁽¹⁾	OVP response time with 100-mV overdrive				1	µs
V_UVP	UVP threshold voltage	UVP detect voltage		79	83	87	%VREF
t_UVPDLY	UVP delay⁽¹⁾	UVP delay				1.5	µs
t_HICDLY	Hiccup delay time	Regular t_SS setting			7 × t_SS		ms
BP LDO REGULATOR
BP	LDO output voltage	V_IN = 12 V, I_LOAD = 0 to 10 mA		4.5	5	5.5	V
V_BPUVLO	BP UVLO threshold voltage	Wakeup			3.32		V
V_BPUVLO	BP UVLO threshold voltage	Shutdown			3.11		V
VLDO_BP	LDO low dropout voltage	V_IN= 4.5 V, I_LOAD= 30 mA, T_A = 25°C				365	mV
I_LDOMAX	LDO overcurrent limit	V_IN= 12 V, T_A = 25°C			100		mA
SYNCHRONIZATION
V_IH(SYNC)	High-level input voltage			2			V
V_IL(SYNC)	Low-level input voltage					0.8	V
t_PSW(SYNC)	Sync input minimum pulse width					100	ns
F_SYNC	Synchronization frequency			300		2000	kHz
F_SYNC	Dual-phase			300		1000	kHz
t_{SYNC to SW}	Sync to SW delay tolerance, percentage from phase-to-phase⁽¹⁾	F_SYNC = 300 kHz to 1 MHz,			10%
t_{Lose_SYNC_delay}	Delay when lose sync clock⁽¹⁾	F_SYNC = 300 kHz			5		µs
THERMAL SHUTDOWN
T_SDN	Built-in thermal shutdown threshold⁽¹⁾	Shutdown temperature		155	165		°C
T_SDN	Built-in thermal shutdown threshold⁽¹⁾	Hysteresis			30		°C

(1) Specified by design. Not production tested.