ZHCSGE0B June 2017 – January 2019 TPS53681
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Supply: Currents, UVLO, and Power-On Reset
- 6.6 References: DAC and VREF
- 6.7 Voltage Sense: AVSP and BVSP, AVSN and BVSN
- 6.8 Telemetry
- 6.9 Input Current Sensing
- 6.10 Programmable Loadline Settings
- 6.11 Current Sense and Calibration
- 6.12 Logic Interface Pins: AVR_EN, AVR_RDY, BVR_EN, BVR_RDY, RESET, VR_FAULT, VR_HOT
- 6.13 I/O Timing
- 6.14 PMBus Address Setting
- 6.15 Overcurrent Limit Thresholds
- 6.16 Switching Frequency
- 6.17 Slew Rate Settings
- 6.18 Ramp Selections
- 6.19 Dynamic Integration and Undershoot Reduction
- 6.20 Boot Voltage and TMAX Settings
- 6.21 Protections: OVP and UVP
- 6.22 Protections: ATSEN and BTSEN Pin Voltage Levels and Fault
- 6.23 PWM: I/O Voltage and Current
- 6.24 Dynamic Phase Add and Drop
- 6.25 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 PMBus Connections
- 7.5.2 PMBus Address Selection
- 7.5.3 Supported Commands
- 7.5.4 Commonly Used PMBus Commands
- 7.5.5 Voltage, Current, Power, and Temperature Readings
- 7.5.6 Input Current Sense and Calibration
- 7.5.7 Output Current Sense and Calibration
- 7.5.8 Output Voltage Margin Testing
- 7.5.9 Loop Compensation
- 7.5.10 Converter Protection and Response
- 7.5.11 Output Overvoltage Protection and Response
- 7.5.12 Maximum Allowed Output Voltage Setting
- 7.5.13 Output Undervoltage Protection and Response
- 7.5.14 Minimum Allowed Output Voltage Setting
- 7.5.15 Output Overcurrent Protection and Response
- 7.5.16 Input Under-Voltage Lockout (UVLO)
- 7.5.17 Input Over-Voltage Protection and Response
- 7.5.18 Input Undervoltage Protection and Response
- 7.5.19 Input Overcurrent Protection and Response
- 7.5.20 Over-Temperature Protection and Response
- 7.5.21 Dynamic Phase Shedding (DPS)
- 7.5.22 NVM Programming
- 7.5.23 NVM Security
- 7.5.24 Black Box Recording
- 7.5.25 Board Identification and Inventory Tracking
- 7.5.26 Status Reporting
-
8 Applications, Implementation, and Layout
- 8.1 Application Information
- 8.2 Typical Application
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
RSB Package
40-Pin QFN
Top View
Thermal pad acts as AGND.
NC = not connected
Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ACSP1 | 23 | I | Current sense input for the channel A. Connect to the IOUT pin of TI smart power stages. Tie the ACSP5, ACSP4, ACSP3, or ACSP2 pin to the V3P3 pin according to Table 1 to disable the corresponding phase. |
| ACSP2 | 24 | ||
| ACSP3 | 25 | ||
| ACSP4 | 26 | ||
| ACSP5 | 27 | ||
| ACSP6/BCSP3 | 28 | Current sense inputs for channel A or channel B based on NVM option. Connect to the IOUT pin of smart power stages. Tie ACSP6/BCSP3 to the 3.3-V supply to disable corresponding phase. | |
| ADDR | 34 | I | Voltage divider to VREF and GND. The voltage level sets the 7-bit PMBus address with an ADC. Address is latched at 3.3-V power up. |
| APWM1 | 8 | O | PWM signal for phase 1 of channel A. |
| APWM2 | 7 | O | PWM signal for phase 2 of channel A. |
| APWM3 | 6 | O | PWM signal for phase 3 of channel A. |
| APWM4 | 5 | O | PWM signal for phase 4 of channel A. |
| APWM5 | 4 | O | PWM signal for phase 5 of channel A. |
| APWM6/BPWM3 | 3 | O | PWM signal for phase 6 of channel A, or phase 3 of channel B, based on the NVM option. |
| ATSEN | 36 | O | Connect to TAO pin of TI smart power stages of Channel A to sense the highest temperature of the power stages and to sense the built-in fault signal from power stages |
| AVR_EN | 13 | I | Active high enable input for channel A. Asserting the AVR_EN pin activates channel A. Re-cycling BVR_EN pin clears the faults of channel A. |
| AVR_RDY | 12 | O | Power good open-drain output signal of channel A. This open drain output requires an external pull-up resistor. The AVR_RDY pin is pulled low when a shutdown fault occurs. |
| AVSN | 22 | I | Negative input of the remote voltage sense of channel A. |
| AVSP | 21 | I | Positive input of the remote voltage sense of channel A. |
| BCSP1 | 32 | I | Current sense input for channel B. Connect to the IOUT pins of TI smart power stages. If channel B is not used, then connect the BCSP1 pin to GND. |
| BCSP2 | 29 | I | Current sense input for channel B. Connect to the IOUT pins of TI smart power stages. Tie the BCSP2 pin to the V3P3 pin according to Table 1 to disable the corresponding phase. |
| BPWM1 | 1 | O | PWM signal for phase 1 of channel B |
| BPWM2 | 2 | O | PWM signal for phase 2 of channel B |
| BTSEN | 35 | O | Connect to TAO pin of TI smart power stages of Channel B to sense the highest temperature of the power stages and to sense the built-in fault signal from power stages |
| BVR_EN | 20 | I | Active high enable input for channel B. Asserting the BVR_EN pin activates channel B. Re-cycling BVR_EN pin clears the faults of channel B. |
| BVR_RDY | 16 | O | Power good open-drain output signal of channel B. This open drain output requires an external pull-up resistor. BVR_RDY is pulled low when a shutdown fault occurs. |
| BVSN | 31 | I | Negative input of the remote voltage sense of channel B. If channel B is not used, connect BVSN to GND. |
| BVSP | 30 | I | Positive input of the remote voltage sense of channel B. If channel B is not used, connect BVSP to GND. |
| CSPIN | 37 | I | Input voltage from the positive terminal connecting to the input current sensing shunt. When input current sensing is not used, short CSPIN to VIN_CSNIN and connect to the converter input voltage (example: 12 V). |
| GND | 17 | G | Connect to GND |
| 18 | |||
| NC | 19 | – | No connection. |
| RESET | 15 | I/O | Resets the output voltage to BOOT voltage |
| SMB_ALERT | 11 | I/O | SMBus or I2C bi-directional ALERT pin interface. (Open drain) |
| SMB_CLK | 10 | I | SMBus or I2C serial clock interface. (Open drain) |
| SMB_DIO | 9 | I/O | SMBus or I2C bi-directional serial data interface. (Open drain) |
| V3P3 | 39 | P | 3.3-V power input. Bypass to GND with a ceramic capacitor with a value greater than or equal to 1 µF. Used to power all digital logic circuits. |
| VIN_CSNIN | 38 | P | Input voltage sensing for on-time control and telemetry. Serves as the negative terminal connecting to the input current sensing shunt. When input current sensing is not used, short VIN_CSNIN to CSPIN and connect to the converter input voltage (example: 12 V). |
| VR_FAULT | 33 | O | VR fault indicator. (Open-drain). The failures include the high-side FETs short, over-voltage, over-temperature, and the input over-current conditions. Use the fault signal on the platform to remove the power source by turning off the AC power supply. When the failure occurs, the VR_FAULT pin is LOW, and put the controller into latch-off mode. One NVM bit is used to select whether or not the faults from channel B asserts the VR_FAULT. pin. |
| VREF | 40 | O | 1.7-V LDO reference voltage. Bypass to GND with 1-µF ceramic capacitor. Connect the VREF pin to the REFIN pin of the TI smart power stages as the current sense common-mode voltage. |
| VR_HOT | 14 | O | Active low external temperature indicator. |
| Thermal Pad | G | Analog ground pad. Connect to GND plan with vias. | |
(1) G = ground, I = input, O = output, P = power input
Table 1. Current Sense Inputs for Active Phases
| Active Phase Channel | ACSP1 | ACSP2 | ACSP3 | ACSP4 | ACSP5 | ACSP6 | BSCP1 | BSCP2 | |
|---|---|---|---|---|---|---|---|---|---|
| A | B | ||||||||
| 1 | 0 | AIOUT1 | V3P3 | n/a | n/a | n/a | n/a | GND | V3P3 |
| 2 | 1 | AIOUT1 | AIOUT2 | V3P3 | n/a | n/a | n/a | BIOUT1 | V3P3 |
| 3 | 1 | AIOUT1 | AIOUT2 | AIOUT3 | V3P3 | n/a | n/a | BIOUT1 | V3P3 |
| 4 | 1 | AIOUT1 | AIOUT2 | AIOUT3 | AIOUT4 | V3P3 | n/a | BIOUT1 | V3P3 |
| 5 | 1 | AIOUT1 | AIOUT2 | AIOUT3 | AIOUT4 | AIOUT5 | V3P3 | BIOUT1 | V3P3 |
| 6 | 0 | AIOUT1 | AIOUT2 | AIOUT3 | AIOUT4 | AIOUT5 | AIOUT6 | GND | V3P3 |
| 6(1) | 1 | AIOUT1 | AIOUT2 | AIOUT3 | AIOUT4 | AIOUT5 | AIOUT6 | BIOUT1 | V3P3 |
| 6 | 2 | AIOUT1 | AIOUT2 | AIOUT3 | AIOUT4 | AIOUT5 | AIOUT6 | BIOUT1 | BIOUT2 |
| 5 | 2 | AIOUT1 | AIOUT2 | AIOUT3 | AIOUT4 | AIOUT5 | V3P3 | BIOUT1 | BIOUT2 |
| 5(1) | 3 | AIOUT1 | AIOUT2 | AIOUT3 | AIOUT4 | AIOUT5 | BIOUT3 | BIOUT1 | BIOUT2 |
(1) For n+1 or n+3 applications, the NVM setting must be changed. See also the Phase Configuration for Channel B section.