ZHCSGE0B June 2017 – January 2019 TPS53681
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Supply: Currents, UVLO, and Power-On Reset
- 6.6 References: DAC and VREF
- 6.7 Voltage Sense: AVSP and BVSP, AVSN and BVSN
- 6.8 Telemetry
- 6.9 Input Current Sensing
- 6.10 Programmable Loadline Settings
- 6.11 Current Sense and Calibration
- 6.12 Logic Interface Pins: AVR_EN, AVR_RDY, BVR_EN, BVR_RDY, RESET, VR_FAULT, VR_HOT
- 6.13 I/O Timing
- 6.14 PMBus Address Setting
- 6.15 Overcurrent Limit Thresholds
- 6.16 Switching Frequency
- 6.17 Slew Rate Settings
- 6.18 Ramp Selections
- 6.19 Dynamic Integration and Undershoot Reduction
- 6.20 Boot Voltage and TMAX Settings
- 6.21 Protections: OVP and UVP
- 6.22 Protections: ATSEN and BTSEN Pin Voltage Levels and Fault
- 6.23 PWM: I/O Voltage and Current
- 6.24 Dynamic Phase Add and Drop
- 6.25 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 PMBus Connections
- 7.5.2 PMBus Address Selection
- 7.5.3 Supported Commands
- 7.5.4 Commonly Used PMBus Commands
- 7.5.5 Voltage, Current, Power, and Temperature Readings
- 7.5.6 Input Current Sense and Calibration
- 7.5.7 Output Current Sense and Calibration
- 7.5.8 Output Voltage Margin Testing
- 7.5.9 Loop Compensation
- 7.5.10 Converter Protection and Response
- 7.5.11 Output Overvoltage Protection and Response
- 7.5.12 Maximum Allowed Output Voltage Setting
- 7.5.13 Output Undervoltage Protection and Response
- 7.5.14 Minimum Allowed Output Voltage Setting
- 7.5.15 Output Overcurrent Protection and Response
- 7.5.16 Input Under-Voltage Lockout (UVLO)
- 7.5.17 Input Over-Voltage Protection and Response
- 7.5.18 Input Undervoltage Protection and Response
- 7.5.19 Input Overcurrent Protection and Response
- 7.5.20 Over-Temperature Protection and Response
- 7.5.21 Dynamic Phase Shedding (DPS)
- 7.5.22 NVM Programming
- 7.5.23 NVM Security
- 7.5.24 Black Box Recording
- 7.5.25 Board Identification and Inventory Tracking
- 7.5.26 Status Reporting
-
8 Applications, Implementation, and Layout
- 8.1 Application Information
- 8.2 Typical Application
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
訂購信息
8.2.1.4 Inductor DCR and Shunt Current Sensing Design for Input Power
This section describes designing the thermal compensation network. The NTC thermistor is used to compensate thermal variations in the resistance of the inductor winding. The winding is usually copper. And as such has a resistance coefficient of 3900 PPM/°C. Alternatively, the NTC thermistor characteristic is very non-linear and requires two or three resistors to linearize them over the range of interest. Figure 73 shows a typical DCR circuit.
Figure 73. Typical DCR Current Sensing Circuit Equation 8 calculates the voltage across the CSENSE capacitor when it exactly equals the voltage across RDCR.
where
- REQ is the series/parallel combination of RSEQU, RNTC, RSERIES and RPAR
Ensure that CSENSE is a capacitor type which is stable over temperature, use X7R or better dielectric (C0G preferred). Because calculating these values by hand can be time-consuming, TI offers a spreadsheet using the Excel Solver function available to provide calculation assistance. Contact your local TI representative to get a copy of the spreadsheet.
This example uses a simple design process to enable input shunt sensing, so no DCR network is needed. Insert a 0.5-mΩ shunt resistor in series between the input inductor and the input bulk capacitors.