| 31-29 |
Reserved |
Reserved. Read only. Always reads as 0. Writes have no effect. |
| 28 |
EMU-RST |
Reset initiated by emulation.
- 0 = Not the last reset to occur.
- 1 = The last reset to occur.
|
| 27-12 |
Reserved |
Reserved. Read only. Always reads as 0. Writes have no effect. |
| 11 |
WDRST3 |
Reset initiated by watchdog timer[N].
- 0 = Not the last reset to occur.
- 1 = The last reset to occur.
|
| 10 |
WDRST2 |
Reset initiated by watchdog timer[N].
- 0 = Not the last reset to occur.
- 1 = The last reset to occur.
|
| 9 |
WDRST1 |
Reset initiated by watchdog timer[N].
- 0 = Not the last reset to occur.
- 1 = The last reset to occur.
|
| 8 |
WDRST0 |
Reset initiated by watchdog timer[N].
- 0 = Not the last reset to occur.
- 1 = The last reset to occur.
|
| 7-3 |
Reserved |
Reserved. Read only. Always reads as 0. Writes have no effect. |
| 2 |
PLLCTLRST |
Reset initiated by PLLCTL.
- 0 = Not the last reset to occur.
- 1 = The last reset to occur.
|
| 1 |
RESET |
RESET reset.
- 0 = RESET was not the last reset to occur.
- 1 = RESET was the last reset to occur.
|
| 0 |
POR |
Power-on reset.
- 0 = Power-on reset was not the last reset to occur.
- 1 = Power-on reset was the last reset to occur.
|