ZHCSSV5 January 2024 TMP119
PRODUCTION DATA
| STANDARD | FAST-MODE | UNIT | |||||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| fSCL | SCL operating frequency | 1 | 1 | 400 | KHz | ||
| tBUF | Bus free time between STOP and START conditions | 1300 | ns | ||||
| tHD;STA | Hold time after repeated START condition. After this period, the first clock is generated(1) |
5 | 600 | ns | |||
| tSU;STA | Repeated START condition setup time | 600 | ns | ||||
| tSU;STO | STOP condition setup time | 600 | ns | ||||
| tHD;DAT | Data hold time | 0 | ns | ||||
| tVD;DAT | Data valid time(2) | 0.9 | μs | ||||
| tSU;DAT | Data setup time | 100 | ns | ||||
| tLOW | SCL clock low period | 1300 | ns | ||||
| tHIGH | SCL clock high period | 600 | ns | ||||
| tF – SDA | Data fall time | 20 × (V+ /5.5) | 300 | ns | |||
| tF, tR – SCL | Clock fall and rise time | 300 | ns | ||||
| tR | Rise time for SCL ≤100 kHz | 1000 | ns | ||||
| Serial bus timeout (SDA bus released if there is no clock) | 20 | 40 | ms | ||||