ZHCSSV5 January 2024 TMP119
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Device Comparison
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 EEPROM Programming
- 7.5.2 Pointer Register
- 7.5.3 I2C and SMBus Interface
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.5.3.1.8 Timing Diagrams
The TMP119 is two-wire, SMBus and I2C interface-compatible. Figure 7-10 to Figure 7-13 show the various operations with the TMP119. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the controller device.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. The user must take setup and hold times into account. On a controller receive, the termination of the data transfer can be signaled by the controller generating a not-acknowledge (1) on the last byte transmitted by the target.
Figure 7-10 Write Word Command Timing Diagram
Figure 7-11 Read Word Command Timing Diagram
Figure 7-12 SMBus ALERT Timing Diagram
Figure 7-13 General-Call Reset Command Timing Diagram