ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
In SPI control mode, the LIMP pin defaults to the limp home function. When fail-safe mode is enabled (default on) the pin behaves the same as stated in pin control mode with the exception of every watchdog error causing a reset. Programming register 8'h1A[3:2], LIMP_SEL_RESET, determines the condition for the LIMP pin to turn off. The three modes that the LIMP pin changes state is normal, fail-safe and standby mode. When in normal and standby mode the LIMP pin is off unless there is a watchdog failure event, which turns on the LIMP pin. When entering these two modes, there is an initial long window requiring a watchdog input trigger. This is treated as a WD failure and LIMP pin turns on if the window is missed. Any event that causes the device to enter fail-safe mode also turns on the LIMP pin. LIMP is turned off once the device enters standby mode from fail-safe mode except for a watchdog error as described previously. When fail-safe mode is disabled, a WD input failure causes the LIMP pin to turn on, and the device enters restart mode.
If the LIMP function is not needed, this pin can be configured to support either a high side switch in SPI mode by using register 8'h1B[7:6] = 01b or to the INH function by setting register 8'h1B[7:6] = 10b. When configured as a high side switch, the pin can support the same load as the HSS pin, but does not have the open load and over current detection features. When used as a high side switch, timing control is configurable using on/off, PWM or timer based. When using PWM, PWM1 or PWM2 can be assigned. When using the timer, timer1 or timer2 and be assigned.