ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
Cyclic sense wake is a method using the high-side switch with the WAKE input pin to periodically check for a WAKE pin state change in standby and sleep modes. In sleep mode, cyclic sense wake reduces the quiescent current of the device by reducing the WAKE circuitry to be active only during the on time of the HSS pin, see Figure 8-48 as an example for this. Periodically, the HSS pin turns on applying VSUP to the external local wake circuitry and the device samples the state of the WAKE pin. Each time the WAKE pin is sampled, the current state is compared to the previous state. If there has been a state change, the device wakes up and transitions to restart mode; otherwise, it remains in sleep mode. See Figure 8-49 for the timing diagram. In standby mode, the same process is followed for determining a state change on the WAKE pin. A state change on the WAKE pin causes the device to initiate an interrupt and the RXD pin is latched low. When entering standby or sleep mode, this process is reset with the first HSS on time being the initial WAKE pin state and does not cause a wake event.
The wake time is based upon tWK_CYC, which is the sampling window, as shown in Static WAKE. This HSS period and on time are determined by setting timer1 register, 8'h25[7:0] or timer 2 register 8'h26[7:0]. The sampling window, tWK_CYC, is determined by register 8'h12[5].