ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
The TLIN1431x-Q1 has a watchdog error counter used in SPI control mode. This counter is an up down counter that increments for every missed window or incorrect input watchdog trigger event. In SPI control, the error counter is set at one by default. The counter decrements for every correct input trigger and increments on every incorrect input trigger, but it never drops below zero. When the programmed counter is reached, the device transitions to restart mode, error counter is reset back to one, and the nRST pin pulls low for tNRST_TOG. At the end of this time, the device transitions back to standby mode releasing the nRST pin to high. This counter can be changed to 1 (every error), 5, 9, or 15 using 8'h16[7:6]. The error counter can be read at register 8'h14[4:1]. In pin control, nWDR is pulled low for every watchdog error.
If the watchdog error count is set at one, the first input failure causes the device to transition to restart. This allows the system to check the counter after the first input trigger to see if a valid input was sent. Every incorrect watchdog input causes the interrupt to be set and nINT is pulled low.