ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The TLIN1431x supports cyclic redundancy check (CRC) for SPI transactions and is default disabled. Register 8'h0A[0] can be used to enable this feature. The default polynomial supports AutoSAR CRC8H2F, X8 + X5 + X3 + X2 + X + 1, see Table 8-7. CRC8 according to SAE J1850 is also supported and can be selected at register 8'h0B[0].
When CRC is enabled, a filler byte of 00h is used to calculate the CRC value during a read/write operation, see Figure 8-52 and Figure 8-53.
| SPI Transactions | |
|---|---|
| CRC result width | 8 bits |
| Polynomial | 2Fh |
| Initial value | FFh |
| Input data reflected | No |
| Result data reflected | No |
| XOR value | FFh |
| Check | DFh |
| Magic Check | 42h |
| SPI Transactions | |
|---|---|
| CRC result width | 8 bits |
| Polynomial | 1Dh |
| Initial value | FFh |
| Input data reflected | No |
| Result data reflected | No |
| XOR value | FFh |
| Check | 4Bh |
| Magic Check | C4h |