ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
PWM1_CNTL2 is shown in Figure 8-76 and described in Table 8-32
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Set the two most significant bit for the 10-bit PWM1. These work with register h'21 PWM1_CNTL3.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PWM1_RSVD | PWM1_DC_MSB | ||||||
| R-0b | R/W-00b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | PWM1_RSVD | R | 0b | Reserved |
| 1-0 | PWM1_DC_MSB | R/W | 00b | Most significant two bits for 10-bit PWM1 duty cycle select. Works with 'h21[7:0] 00b = 100% off when used with 'h21[7:0] and it is 00h xxb = on time with an increase of ~ 0.1% when used with 'h21[7:0] 11b = 100% of when used with 'h21[7:0] and it is FFh |
Minimum on-time during PWM is limited to the on and off-time of the high side switch. This will make certain PWM values unusable like 00 0000 0001.