ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
INT_EN_2 is shown in Figure 8-90 and described in Table 8-46.
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Interrupt mask for INT_2.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | OVCC_EN | UVSUP_EN | RSVD | UVCC_EN | TSD_VCC_LIN_EN | TSD_HSS_LMIP_EN | |
| R-0b | R/W-1b | R/W-1b | R-0b | R/W-1b | R/W-1b | R/W-1b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RSVD | R | 0b | Reserved |
| 5 | OVCC_EN | R/W | 1b | VCC over voltage enable |
| 4 | UVSUP_EN | R/W | 1b | VSUP undervoltage enable |
| 3 | RSVD | R | 0b | Reserved |
| 2 | UVCC_EN | R/W | 1b | VCC undervoltage enable |
| 1 | TSD_VCC_LIN_EN | R/W | 1b | Thermal shutdown enable for VCC and LIN |
| 0 | TSD_HSS_LIMP_EN | R/W | 1b | Thermal shutdown due to HSS or LIMP enable |