ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
When configured for pin control, the WDT or CLK pin becomes the pin programmable watchdog delay input, WDT. This pin sets the upper boundary of the window watchdog. It can be connected to VCC, connected to GND, or left floating. When connected directly to VCC or GND or left open, the window frame takes on one of three value ranges: GND – 32 ms to 48 ms, VCC – 480 ms to 720 ms or left open – 4.8 s to 7.2 s. The closed versus open windows are based upon 50%/50%.
When configured for SPI control, the WDT/CLK pin becomes the SPI input clock, CLK. When configured as the CLK pin there is a 240 kΩ pull-up to VINT enabled.