ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
INT_EN_3 is shown in Figure 8-91 and described in Table 8-47.
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Interrupt mask for INT_3.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPIERR_EN | RSVD | FSM_EN | CRCERR_EN | VCCSC_EN | RSRT_CNT_EN | RSVD | |
| R/W-1b | R-0b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SPIERR_EN | R/W | 1b | SPI error interrupt enable |
| 6 | RSVD | R | 0b | Reserved |
| 5 | FSM_EN | R/W | 1b | Fail-safe mode interrupt enable |
| 4 | CRCERR_EN | R/W | 1b | SPI CRC error interrupt enable |
| 3 | VCCSC_EN | R/W | 1b | VCC short circuit interrupt enable |
| 2 | RSRT_CNT_EN | R/W | 1b | Exceeding programmed restart counter interrupt enable |
| 1-0 | RSVD | R | 0b | Reserved |