ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
INT_3 is shown in Figure 8-88 and described in Table 8-44.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPIERR | RSVD | FSM | CRCERR | VCCSC | RSRT_CNT | RSVD | |
| R/W1C-0b | R-0b | R/W1C-0b | R/W1C/U-0b | R/W1C/U-0b | R/W1C/U-0b | R-0b | |
| Bit | Field | Type | Reset | Description0b |
|---|---|---|---|---|
| 7 | SPIERR | R/W1C | 0b | Sets when SPI status bit sets |
| 6 | RSVD | R | 0b | Reserved |
| 5 | FSM | R/W1C | 0b | Entered fail-safe mode. Can be cleared while in failsafe mode. |
| 4 | CRCERR | R/W1C/U | 0b | SPI CRC error detected |
| 3 | VCCSC | R/W1C/U | 0b | VCC short detected |
| 2 | RSRT_CNT | R/W1C/U | 0b | Restart counter exceeded programmed count |
| 1-0 | RSVD | R | 0b | Reserved |