ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
Upon initialization GPIO0 through GPIO6 are enabled as inputs by default. Each GPIO pin has an input disable and a pulldown disable control bit, with the exception of GPIO3 which is open drain. By default, the GPIO pin input paths are enabled and the internal pulldown circuit for the GPIO is enabled. The GPIO_INPUT_CTL (0x0F) and GPIO_PD_CTL (0xBE) registers allow control of the input enable and the pulldown, respectively. For example, to disable GPIO1 and GPIO2 as inputs the user would program in register 0x0F[2:1] = 11. For most applications, there is no need to modify the default register settings for the pulldown resistors. The status HIGH or LOW of each GPIO pin 0 through 6 may be read through the GPIO_PIN_STS register 0x0E. This register read operation provides the status of the GPIO pin independent of whether the GPIO pin is configured as an input or output.