ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
The V3Link receiver also checks the decoded data for encoding or sequence errors in the received V3Link frame. If either of these error conditions are detected the V3LINK_ENC_ERROR bit will be latched in the RX_PORT_STS2 register 0x4E[5]. An interrupt may also be generated based on assertion of the encoded error flag. To detect V3Link Encoder errors, the LINK_ERROR_COUNT must be enabled with a LINK_ERR_THRESH value greater than 1. Otherwise, the loss of Receiver Lock will prevent detection of the Encoder error. The V3LINK_ENC_ERROR flag is cleared on read.
When partnered with a TSER953, the V3LINK Encoder may be configured to include a CRC check of the V3LINK encoder sequence. The CRC check provides an extra layer of error checking on the encoder sequence. This CRC checking adds protection to the encoder sequence used to send link information comprised of Datapath Control (registers 0x59 and 0x5A), Sensor Status (registers 0x51-0x54), and Serializer ID (register 0x5B). TI recommends enabling the CRC error checking on the V3LINK Encoder sequence to prevent any updates of link information values from encoded packets that do not pass CRC check. The V3LINK Encoder CRC is enabled by setting the V3LINK_ENC_CRC_DIS (register 0xBA[7] Table 7-151) to 0. In addition, the V3LINK_ENC_CRC_CAP flag should be set in register 0x4A[4] (see Section 7.6.66).