ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
Figure 6-1 LVCMOS Transition Times
Figure 6-2 V3Link Receiver VID, VIN, VCM
Figure 6-3 Deserializer Data Lock Time
Figure 6-4 I2C Serial Control Bus Timing
Figure 6-5 Clock and Data Timing in HS Transmission
Figure 6-6 High-Speed Data Transmission Burst
Figure 6-7 Switching the Clock Lane Between Clock Transmission and Low-Power Mode
Figure 6-8 Long Line Packets and Short Frame Sync Packets
Figure 6-9 CSI-2 General Frame Format
Figure 6-10 MIPI CSI-2 Data Lane Configuration