Routing the V3Link signal traces between the RIN pins and the connector as well as connecting the PoC filter to these traces are the most critical pieces of a successful TDES954 PCB layout. Figure 10-1 shows an example PCB layout of the TDES954 configured for interface to remote sensor modules over coaxial cables. The layout example also uses a footprint of an edge-mount FAKRA connector provided by Rosenberger (P/N: 59S20X-40ML5-Z). The DS90UB954-Q1 EVM can be used to evaluate the TDES954. For additional PCB layout details of the example, check the DS90UB954-Q1 EVM User's Guide.
The following list provides essential recommendations for routing the signal traces between the DS90UB954-Q1 EVM receiver input pins (RIN) and the FAKRA connector, and connecting the PoC filter.
- The routing of the traces may be all on the top layer (as shown in the example) or partially embedded in middle layers if EMI is a concern
- The AC-coupling capacitors should be on the top layer and very close to the DS90UB954-Q1 EVM receiver input pins to minimize the length of coupled differential trace pair between the pins and the capacitors.
- Route the RIN+ trace between the AC-coupling capacitor and the FAKRA connector as a 50-Ω single-ended micro-strip with tight impedance control (±10%). Calculate the proper width of the trace for a 50-Ω impedance based on the PCB stack-up. Ensure that the trace can carry the PoC current for the maximum load presented by the remote sensor module.
- The PoC filter should be connected to the RIN+ trace through the first ferrite bead (FB1). The FB1 should be touching the high-speed trace to minimize the stub length seen by the transmission line. Create an anti-pad or a moat under the FB1 pad that touches the trace. The anti-pad should be a plane cutout of the ground plane directly underneath the top layer without cutting out the ground reference under the trace. The purpose of the anti-pad is to maintain the impedance as close to 50 Ω as possible.
- Route the RIN– trace loosely coupled to the RIN+ trace for the length similar to the RIN+ trace length when possible. This will help the differential nature of the receiver to cancel out any common-mode noise that may be present in the environment that may couple on to the RIN+ and RIN– signal traces. When routing on inner layers, length matching for single-ended traces does not provide as significant benefit.
When configured for STP and routing differential signals to the TDES954 receiver inputs, the traces should maintain 100-Ω differential impedance routed to the connector. When choosing to implement a common mode choke for common mode noise reduction, take care to minimize the effect of any mismatch. Figure 10-2 shows an example PCB layout for STP configuration.